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1919 Commits

Author SHA1 Message Date
Roland Coeurjoly 547c5466ec Ignore smt2 files, generated by the execution of the tests 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 54225b5c42 Add test for SMT backend. Tests if SMT is valid and compares simulation with yosys sim 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 720429b1fd Add test_cell tests for C++ functional backend 2024-08-21 11:01:09 +01:00
Emil J e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix 
peepopt: avoid shift-amount underflow
 2024-08-19 15:45:46 +02:00
Miodrag Milanovic 54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 3848563600 Update tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 34f08bc639 Enable nanoxplore tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 65d2ebac9d fix test 2024-08-15 17:50:36 +02:00
Lofty b0c4add642 Added lutram 2024-08-15 17:50:36 +02:00
Lofty b3f59c9820 Add NX_CY 2024-08-15 17:50:36 +02:00
Lofty b4e9bb0d85 Add FFs and related tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b4a17cccc3 add few more tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 93543bd874 add lut tests 2024-08-15 17:50:36 +02:00
Martin Povišer c35f5e379c Extend liberty tests 2024-08-13 18:47:36 +02:00
George Rennie b6ceff2aab peepopt clockgateff: add testcase 2024-08-07 10:21:52 +01:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J. Tywoniak 01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
chunlin min 3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init 2024-07-08 17:03:03 -04:00
Tony Min d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
Tony Min 6fe0e00050
Add missing u sram init (#3) 
add missing INIT for uSRAM
 2024-07-04 16:39:10 -04:00
chunlin min 8e7ec2d660 add assertions for synth_microchip tests 2024-07-04 15:45:44 -04:00
chunlin min e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip 2024-07-04 14:16:52 -04:00
phsauter 34b5c6d062 peepopt: avoid shift-amount underflow 2024-06-13 23:30:07 +02:00
Marian Buschsieweke 7f89a45ad7 cxxxrtl: fix use of format specifiers in test 
This fix a few instances of incorrect (and non-portable) use of format
specifiers.
 2024-06-11 07:22:39 +01:00
Asherah Connor dc69365258 cxxrtl: failing test: unconnected blackbox outputs don't compile. 2024-06-07 14:24:27 +03:00
Martin Povišer 4b67f3757f
Merge pull request #4404 from YosysHQ/povik/bbox_derive 
box_derive: New command to derive modules for boxes
 2024-05-31 19:09:18 +02:00
Martin Povišer 97fedff383 box_derive: Tune the test 2024-05-29 20:42:11 +02:00
Martin Povišer bff2443af8 box_derive: Finish the test 2024-05-21 16:34:49 +02:00
Martin Povišer c0a196173a Rename `bbox_derive` to `box_derive` 2024-05-21 16:18:03 +02:00
N. Engelhardt 24f9329c67
Merge pull request #4367 from YosysHQ/lofty/intel_alm-drop-quartus 
intel_alm: drop quartus support
 2024-05-21 16:01:23 +02:00
Martin Povišer 557db4ea46 bbox_drive: Add an incomplete test 2024-05-21 14:57:49 +02:00
Martin Povišer b143e5678f cellmatch: Rename the special design to `$cellmatch` 2024-05-03 16:42:41 +02:00
Martin Povišer 913bc87c44 cellmatch: Add test 2024-05-03 16:42:41 +02:00
Emil J. Tywoniak a833f05036 techmap: add dynamic cell type test 2024-05-03 13:53:49 +02:00
Lofty 8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
N. Engelhardt e8ec19c273 add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality) 2024-04-12 13:51:06 +02:00
N. Engelhardt b87327d1b9 fix hierarchy -generate mode handling of cells 2024-04-12 13:38:33 +02:00
Miodrag Milanovic 0c7ac36dcf Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
Martin Povišer dc746080f5
Merge pull request #4298 from povik/kogge-stone 
techmap: Add a Kogge-Stone option for `$lcu` mapping
 2024-04-08 16:46:06 +02:00
N. Engelhardt 8e8885e1cc
Merge pull request #4323 from YosysHQ/tests_update 
Tests update for latest more strict iverilog
 2024-04-08 15:10:59 +02:00
Miodrag Milanovic 4ac10040ce Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00
Miodrag Milanovic 91e41d8c80 Move parameters to module declaration 2024-04-08 12:44:37 +02:00
Catherine d9a4a42389 write_verilog: don't `assign` to a `reg`. 
Fixes #2035.
 2024-04-03 13:06:45 +02:00
Merry d07a55a852 cxxrtl: Fix sdivmod 
x = x.neg(); results in the subsequent x.is_neg() always being false.
Ditto for the dividend.is_neg() != divisor.is_neg() test.
 2024-03-30 07:56:11 +00:00
Martin Povišer c49d6e7874 techmap: Add Kogge-Stone test 2024-03-27 11:08:26 +01:00
Martin Povišer 5924d97381 tests: Remove part of test involving combinational loops 2024-03-11 10:45:36 +01:00
Martin Povišer 87e72ef86f celledges: Add read ports arst paths 2024-03-11 10:45:17 +01:00
Martin Povišer e4296072c4 check: Rephrase regex for portability 2024-03-11 10:45:17 +01:00
Martin Povišer e1e77a7fa9 check: Extend testing 2024-03-11 10:45:17 +01:00
Martin Povišer 3eef6450f1 check: Add coarse-grain false positive test 2024-03-11 10:43:49 +01:00
N. Engelhardt d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops 
celledges: support shift ops
 2024-03-08 09:35:47 +01:00
Jannis Harder 0db76c6ec4 tests/sva: Skip sva tests that use SBY until SBY is compatible again 
This commit is part of a PR that requires corresponding changes in SBY.
To prevent CI failures, detect whether those changes already landed and
skip the SBY using tests until then.
 2024-03-05 14:37:33 +01:00
Roland Coeurjoly 4a2fb18718 Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc 2024-02-25 17:23:56 +01:00
Miodrag Milanović bc8a3a5b18
Merge pull request #4219 from rovinski/master 
dfflibmap: Add a -dont_use flag to ignore cells
 2024-02-20 12:43:44 +01:00
Austin Rovinski 689feed012 dfflibmap: Add a -dont_use flag to ignore cells 
This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-19 13:00:18 -05:00
Martin Povišer db947e4c71
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch 
proc_rom: don't assert on big actionless switch.
 2024-02-19 16:21:40 +01:00
N. Engelhardt edd154e3cd
Merge pull request #4215 from povik/xprop-race 
Address race in `xprop` tests
 2024-02-19 16:16:16 +01:00
Amelia Cuss bf4a46ccb3 proc_rom: don't assert on big actionless switch. 
See the test case.  PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:

ERROR: Assert `width != 0' failed in kernel/mem.cc:518.

Ensure we don't proceed if there's nothing to encode.
 2024-02-18 01:33:28 +11:00
Jannis Harder 811b7b54d4
Merge pull request #4204 from YosysHQ/micko/gen_test 
do not override existing shell variable
 2024-02-16 14:28:56 +01:00
Martin Povišer e51c77484a tests: Comment on `A[0]` 2024-02-16 11:43:28 +01:00
Martin Povišer 5a05344d9c tests: Fix initialization race in xprop tests 2024-02-16 11:43:28 +01:00
Jannis Harder bbdfcfdf30 clk2fflogic: Fix handling of $check cells 
Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.

Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
 2024-02-14 11:42:27 +01:00
Miodrag Milanovic 353ccc9e58 do not override existing shell variable 2024-02-12 12:58:13 +01:00
Miodrag Milanović edb95c69a9
Merge pull request #4084 from jix/scopeinfo 
$scopeinfo support
 2024-02-12 09:51:22 +01:00
Miodrag Milanovic 10297127be fix test for verific 2024-02-12 09:19:58 +01:00
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem a4ae773150 Added test for multidimensional packed arrays 2024-02-11 11:26:52 -05:00
Dag Lem e0d3977e19 Add support for $dimensions and $unpacked_dimensions 2024-02-11 11:26:52 -05:00
Dag Lem 2125357e76 Add support for $increment 2024-02-11 11:26:52 -05:00
Dag Lem a32d9b6c45 Fix test of memory vs. memory converted to registers 
The purpose of memtest02 in tests/simple/memory.v is to	test bit
select on both memory (mem1) and memory converted to registers (mem2).

After 7cfae2c52, mem1 was automatically converted to registers,
and the test no longer worked as intended. This is fixed by
adding (* nomem2reg *) to mem1.
 2024-02-11 11:26:52 -05:00
Dag Lem 39fea32c6e Add support for packed multidimensional arrays 
* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
 2024-02-11 11:26:52 -05:00
Thomas Watson 10e06f9b66 tests/various/clk2fflogic_effects.sh: remove /tmp use 
Might not be accessible.
 2024-02-10 15:09:54 -06:00
Thomas Watson b1f8308772 tests/various/clk2fflogic_effects.sh: fix tail invocation 
Previous syntax is a GNU extension and not accepted by macOS. Use
documented -n option instead, compatible with POSIX-compliant tail
implementations.
 2024-02-10 15:07:55 -06:00
Jannis Harder 9288107f43 Test flatten and opt_clean's $scopeinfo handling 2024-02-06 17:51:29 +01:00
Miodrag Milanović 269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop 
hierarchy: Without a known top module, derive all deferred modules
 2024-02-06 12:08:01 +01:00
Miodrag Milanovic d00843d436 Add -nordff to test 2024-02-06 10:36:30 +01:00
Jannis Harder 0470cbb00d hierarchy: Without a known top module, derive all deferred modules 
This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
 2024-02-06 10:31:40 +01:00
Jannis Harder ffb82df33c Additional tests for FV $check compatibility 2024-02-02 16:07:10 +01:00
Jannis Harder e1a59ba80b async2sync, clk2fflogic: Add support for $check and $print cells 2024-02-01 20:10:39 +01:00
Jannis Harder 331ac5285f tests: Run async2sync before sat and/or sim to handle $check cells 
Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
 2024-02-01 16:14:11 +01:00
Jannis Harder 2baa578d94 Remove too fragile smtlib2_module test 
This compares the write_smt2 output pretty much verbatim, which contains
auto generated private names and fixes an arbitrary ordering. The tested
functionality is also covered by SBY tests which actually interpret the
write_smt2 output using an SMT solver and thus are much more robust, so
we can safely remove this test.
 2024-02-01 16:14:11 +01:00
Martin Povišer ea3dc7c1b4 rtlil: Add wire deletion test 2024-01-29 11:25:54 +01:00
Martin Povišer 08fd47e970 Test roundtripping some processes to Verilog and back 2024-01-24 16:32:25 +00:00
Catherine fc5ff7a265 cxxrtl: always lazily format print messages. 
This is mostly useful for collecting coverage for the future `$check`
cell, where, depending on the flavor, formatting a message may not be
wanted even for a failed assertion.
 2024-01-19 18:55:23 +00:00
Catherine b74d33d1b8 fmt: rename TIME to VLOG_TIME. 
The behavior of these format specifiers is highly specific to Verilog
(`$time` and `$realtime` are only defined relative to `$timescale`)
and may not fit other languages well, if at all. If they choose to use
it, it is now clear what they are opting into.

This commit also simplifies the CXXRTL code generation for these format
specifiers.
 2024-01-19 15:12:05 +00:00
Martin Povišer cb86efa50c celledges: Add test of shift cells edge data 2024-01-19 11:14:10 +01:00
N. Engelhardt 242ae4ef01
Merge pull request #4135 from YosysHQ/verific_clocking_fix 
Fix verific clocking when no driver exist
 2024-01-18 15:40:35 +01:00
Miodrag Milanovic 1764c0ee3c Fix verific clocking when no driver exist 2024-01-18 08:47:04 +01:00
Catherine a33acb7cd9 cxxrtl: refactor the formatter and use a closure. 
This commit achieves three roughly equally important goals:
1. To bring the rendering code in kernel/fmt.cc and in cxxrtl.h as close
   together as possible, with an ideal of only having the bigint library
   as the difference between the render functions.
2. To make the treatment of `$time` and `$realtime` in CXXRTL closer to
   the Verilog semantics, at least in the formatting code.
3. To change the code generator so that all of the `$print`-to-`string`
   conversion code is contained inside of a closure.

There are two reasons to aim for goal (3):
a. Because output redirection through definition of a global ostream
   object is neither convenient nor useful for environments where
   the output is consumed by other code rather than being printed on
   a terminal.
b. Because it may be desirable to, in some cases, ignore the `$print`
   cells that are present in the netlist based on a runtime decision.
   This is doubly true for an upcoming `$check` cell implementing
   assertions, since failing a `$check` would by default cause a crash.
 2024-01-16 16:35:51 +00:00
Dag Lem e0566eafdb Add test for rhs sign extension in array slice assignment 2024-01-10 21:15:00 +01:00
Dag Lem dbec704b49 Include x bits in test of lhs dynamic part-select 2024-01-10 20:28:36 +01:00
Dag Lem a105d2c050 Add torture test for (* nowrshmsk *) stride optimization 2024-01-10 20:28:36 +01:00
Dag Lem 2cab4ff173 Correction and optimization of nowrshmsk 
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that
nowrshmsk is actually tested.

Stride is extracted from indexing of two-dimensional packed arrays and
variable slices on the form dst[i*stride +: width] = src, and is used
to optimize the generated CASE block.

Also uses less confusing variable names for indexing of lhs wires.
 2024-01-10 20:28:36 +01:00
Dag Lem 1bbea13f80 Correct hierarchical path names for structs and unions 2024-01-04 17:22:07 +01:00
N. Engelhardt d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash 
tests: use /usr/bin/env for bash.
 2023-12-18 16:33:35 +01:00
Martin Povišer 449e3dbbd3 cxxrtl: Mask `bmux` result appropriately 2023-12-14 06:57:28 +00:00
Merry 1dff3c83d9 tests/cxxrtl: Add -O2 2023-12-13 12:27:06 +00:00
Merry 29e0cc6acd cxxrtl: Add simple fuzzing tests for value 2023-12-13 12:21:44 +00:00
Merry d7cb6981b5 cxxrtl: Fix value::ctlz 2023-12-13 12:21:44 +00:00
Merry ded63bedd5 cxxrtl: Fix value::sshr 2023-12-13 12:11:57 +00:00
Merry ff53f3d2b6 cxxrtl: Fix value::shl 2023-12-13 12:02:30 +00:00
Jannis Harder 7b74caa5db peepopt: Fix padding for the peepopt_shiftmul_right pattern 
The previous version could easily generate a large amount of padding
when the constant factor was significantly larger than the width of the
shift data input. This could lead to huge amounts of logic being
generated before then being optimized away at a huge performance and
memory cost.

Additionally and more critically, when the input width was not a
multiple of the constant factor, the input data was padded with 'x bits
to such a multiple before interspersing the 'x padding needed to align
the selectable windows to power-of-two offsets.

Such a final padding would not be correct for shifts besides $shiftx,
and the previous version did attempt to remove that final padding at the
end so that the native zero/sign/x-extension behavior of the shift cell
would be used, but since the last selectable window also got
power-of-two padding appended after the padding the code is trying to
remove got added, it did not actually fully remove it in some cases.

I changed the code to only add 'x padding between selectable windows,
leaving the last selectable window unpadded. This omits the need to add
final padding to a multiple of the constant factor in the first place.
In turn, that means the only 'x bits added are actually impossible to
select. As a side effect no padding is added when the constant factor is
equal to or larger than the width of the shift data input, also solving
the reported performance bug.

This fixes #4056
 2023-12-06 18:35:44 +01:00
Martin Povišer 22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
Krystine Sherwin e5c32f399a synth_quicklogic: Testing double_sync_ram_tdp 2023-12-04 15:52:03 +01:00
Krystine Sherwin 97354782c0 Adding double_sync_ram_tdp to blockram.v 2023-12-04 15:52:03 +01:00
Krystine Sherwin 215a777eb3 qlf_tests: minor adjustment 
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
 2023-12-04 15:52:03 +01:00
N. Engelhardt 33ca6994b7 remove example test 2023-12-04 15:52:03 +01:00
N. Engelhardt 3c5b0ab164 fix test setup for synth_quicklogic memory tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 509d176523 attempting to sim split memory tests 
and failing
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 0d1668c1ee QLF_TDP36K: asymmetric simulation tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 497cd021af QLF_TDP36K: truncation tests matter 
Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 7f12d0ba95 QLF_TDP36K: more basic tdp/sdp sim tests 
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 3d08ed216d QLF_TDP36K: parameterised sim test gen 
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin ba3be3fd1c QLF_TDP36K: test bram_tdp post synth 2023-12-04 15:52:03 +01:00
N. Engelhardt f9c8978128 add example memory test 2023-12-04 15:52:03 +01:00
Krystine Sherwin ede4eaeee2 quicklogic: wildcard asymmetric memory tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin 8ded7020f4 tests: asymmetric sync rams now correctly asymmetric 
Also both use the same named parameters for better mirroring.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin ba09866217 quicklogic: testing port widths on split rams 2023-12-04 15:52:03 +01:00
Krystine Sherwin 1a843b2a86 quicklogic: testing 1:4 assymetric memory 2023-12-04 15:52:03 +01:00
Krystine Sherwin 7513bfcbfe quicklogic: fix double width read 2023-12-04 15:52:03 +01:00
Krystine Sherwin 8d3b238b9b quicklogic: Testing split TDP36K 
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
 2023-12-04 15:52:03 +01:00
Krystine Sherwin 991850e1c9 quicklogic: Initial blockram tests 
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
 2023-12-04 15:52:03 +01:00
Martin Povišer a5c8d246f7 quicklogic: Add k6n10f DSP test 2023-12-04 15:52:03 +01:00
Martin Povišer db9e5b4f14 quicklogic: Fix `dffs.ys` test 2023-12-04 15:52:03 +01:00
Martin Povišer 554d8caef7 quicklogic: Add basic k6n10f tests 2023-12-04 15:52:03 +01:00
Martin Povišer 6672b6c1b3 quicklogic: Move pp3 tests one level down 2023-12-04 15:52:02 +01:00
N. Engelhardt 98769010af synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
Catherine 62bbd086b1 cxxrtl: reorganize runtime component files. 
In preparation for substantial expansion of CXXRTL's runtime, this commit
reorganizes the files used by the implementation. Only minimal changes are
required in a consumer.

First, change:
  -I$(yosys-config --datdir)/include
to:
  -I$(yosys-config --datdir)/include/backends/cxxrtl/runtime

Second, change:
  #include <backends/cxxrtl/cxxrtl.h>
to:
  #include <cxxrtl/cxxrtl.h>
(and do the same for cxxrtl_vcd.h, etc.)
 2023-11-28 15:32:36 +00:00
Lofty 7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
N. Engelhardt 63cec22a0c
Merge pull request #3883 from phsauter/peepopt-shiftadd 
peepopt: Add `shiftadd` pattern
 2023-11-07 10:42:15 +01:00
phsauter c3b8de54da test: add tests for `shiftadd` and `shiftmul` 
This expands the part-select tests with one additional module.
It specifically tests the different variants of the `peepopt`
optimizations `shiftadd` and `shiftmul`.
Not all these cases are actually transformed using `shiftadd`,
including them also checks if the correct variants are rejected.
 2023-11-06 14:01:37 +01:00
Lofty b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default" 2023-11-03 14:52:52 +00:00
Lofty 32082477b5 ice40, ecp5: enable ABC9 by default 2023-11-03 08:52:54 +00:00
N. Engelhardt 833b67af80 verific: import attributes on ports 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
 2023-10-20 18:31:41 +02:00
N. Engelhardt 1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Martin Povišer 62d6338688 quicklogic: Fix pp3 `dffs` test 
Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
 2023-10-12 12:45:40 +02:00
Martin Povišer 4506e11d0f booth: Extend test to catch bug from previous commit 2023-10-04 23:30:29 +02:00
Jannis Harder c174597014 Fix sva_value_change_changed test for updated verific 2023-10-03 11:46:43 +02:00
Martin Povišer b0045300fd booth: Cut down the test 
Cut the test down from taking ~25 s to ~3 s.
 2023-09-28 11:55:51 +02:00
Martin Povišer c4762d930e
Merge pull request #3930 from povik/verific-test-memsemantics 
verific: Add test of accurate semantics in memory inference
 2023-09-20 11:46:42 +02:00
Martin Povišer 99a5773911
Merge pull request #3920 from zachjs/asgn-expr 
sv: support assignments within expressions
 2023-09-20 11:30:14 +02:00
Zachary Snow 28e99f2b8c fix width of post-increment/decrement expressions 2023-09-18 23:46:06 -04:00