mirror of https://github.com/YosysHQ/yosys.git
QLF_TDP36K: truncation tests matter
Expected values are now stored in full precision rather than truncating to the same value as the input. i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
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@ -3,10 +3,11 @@ module TB(input clk);
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parameter ADDRESS_WIDTH = 10;
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parameter DATA_WIDTH = 36;
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parameter VECTORLEN = 16;
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localparam MAX_WIDTH = 36;
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reg rce_a_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0];
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reg [DATA_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
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reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
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reg wce_a_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0];
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@ -14,7 +15,7 @@ reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0];
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reg rce_b_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0];
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reg [DATA_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
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reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
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reg wce_b_testvector [VECTORLEN-1:0];
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reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0];
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@ -43,7 +44,7 @@ end
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wire rce_a = rce_a_testvector[i];
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wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i];
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wire [DATA_WIDTH-1:0] rq_a_e = rq_a_expected[i];
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wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i];
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wire [DATA_WIDTH-1:0] rq_a;
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wire wce_a = wce_a_testvector[i];
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@ -52,7 +53,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i];
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wire rce_b = rce_b_testvector[i];
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wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i];
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wire [DATA_WIDTH-1:0] rq_b_e = rq_b_expected[i];
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wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i];
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wire [DATA_WIDTH-1:0] rq_b;
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wire wce_b = wce_b_testvector[i];
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