mirror of https://github.com/YosysHQ/yosys.git
quicklogic: Testing split TDP36K
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories. Refactor python blockram template to take a list of params to support the above. Also change the smaller single TDP36K tests to also test `port_a_width` value.
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@ -96,6 +96,46 @@ module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra
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endmodule // sync_ram_sdp_wrr
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module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10)
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(
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input wire write_enable_a, clk_a,
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input wire [DATA_WIDTH_A-1:0] data_in_a,
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input wire [ADDRESS_WIDTH_A-1:0] address_in_r_a, address_in_w_a,
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output wire [DATA_WIDTH_A-1:0] data_out_a,
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input wire write_enable_b, clk_b,
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input wire [DATA_WIDTH_B-1:0] data_in_b,
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input wire [ADDRESS_WIDTH_B-1:0] address_in_r_b, address_in_w_b,
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output wire [DATA_WIDTH_B-1:0] data_out_b
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);
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sync_ram_sdp #(
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.DATA_WIDTH(DATA_WIDTH_A),
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.ADDRESS_WIDTH(ADDRESS_WIDTH_A)
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) a_ram (
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.write_enable(write_enable_a),
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.clk(clk_a),
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.data_in(data_in_a),
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.address_in_r(address_in_r_a),
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.address_in_w(address_in_w_a),
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.data_out(data_out_a)
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);
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sync_ram_sdp #(
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.DATA_WIDTH(DATA_WIDTH_B),
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.ADDRESS_WIDTH(ADDRESS_WIDTH_B)
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) b_ram (
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.write_enable(write_enable_b),
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.clk(clk_b),
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.data_in(data_in_b),
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.address_in_r(address_in_r_b),
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.address_in_w(address_in_w_b),
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.data_out(data_out_b)
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);
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endmodule // double_sync_ram_sdp
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module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk_a, clk_b,
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input wire write_enable_a, write_enable_b,
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@ -1,51 +1,74 @@
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blockram_template = """\
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blockram_template = """# ======================================
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design -reset; read_verilog -defer ../../common/blockram.v
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chparam -set ADDRESS_WIDTH {aw} -set DATA_WIDTH {dw} {top}
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chparam{param_str} {top}
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hierarchy -top {top}
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synth_quicklogic -family qlf_k6n10f -top {top}; cd {top}
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log TESTING aw:{aw} dw:{dw} top:{top}\
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log ** TESTING {top} WITH PARAMS{param_str}\
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"""
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blockram_tests: "list[tuple[int, int, str, list[str]]]" = [
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blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
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# TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work
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(10, 36, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(11, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(12, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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# larger sizes need an extra ram
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(10, 48, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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(11, 36, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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(12, 18, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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(12, 10, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 48)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 10)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]),
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# 4096x20bit *can* fit in 3, albeit somewhat awkwardly
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(12, 20, "sync_ram_*dp", ["-assert-min 3 t:TDP36K",
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"-assert-max 4 t:TDP36K"]),
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# smaller sizes can still fit in one
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(10, 32, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(10, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(10, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(11, 16, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(11, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(12, 8, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(13, 4, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(14, 2, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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(15, 1, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_*dp", ["-assert-min 3 t:TDP36K",
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"-assert-max 4 t:TDP36K"]),
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# smaller sizes can still fit in one, and assign the correct width (1, 2, 4, 8, 18 or 36)
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 24)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
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([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]),
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([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 4)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=4 %i"]),
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([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]),
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([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]),
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# 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K)
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(11, 18, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
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(11, 9, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
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# 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K)
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(11, 18, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
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(10, 36, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
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# two disjoint 18K memories can share a single TDP36K
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
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("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16),
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("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
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([("ADDRESS_WIDTH_A", 14), ("DATA_WIDTH_A", 1),
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("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]),
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# but only if data width is <= 18
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([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36),
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("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]),
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# sharing a TDP36K sets is_split=1
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([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18),
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("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]),
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# an unshared TDP36K sets is_split=0
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([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]),
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]
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with open("t_mem.ys", mode="w") as f:
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for (aw, dw, top, assertions) in blockram_tests:
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for (params, top, assertions) in blockram_tests:
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param_str = ""
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for (key, val) in params:
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param_str += f" -set {key} {val}"
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if "*" in top:
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star_sub = ["s", "t"]
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else:
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star_sub = [""]
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for sub in star_sub:
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print(
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blockram_template.format(aw=aw, dw=dw, top=top.replace("*", sub)),
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blockram_template.format(param_str=param_str, top=top.replace("*", sub)),
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file=f
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)
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for assertion in assertions:
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print("select {}\n".format(assertion), file=f, end=None)
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print("select {}".format(assertion), file=f)
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print("", file=f)
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