quicklogic: Initial blockram tests

Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.

tests/arch/common/blockram.v

@@ -45,6 +45,57 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
 endmodule // sync_ram_sdp
 
 
+module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // wd=16, wa=9
+   (input  wire                          clk, write_enable,
+    input  wire  [(DATA_WIDTH*2)-1:0]    data_in,
+    input  wire  [ADDRESS_WIDTH-2:0]     address_in_w,
+    input  wire  [ADDRESS_WIDTH-1:0]     address_in_r,
+    output wire  [DATA_WIDTH-1:0]        data_out);
+
+  localparam WORD  = ((DATA_WIDTH*2)-1);
+  localparam DEPTH = (2**(ADDRESS_WIDTH-1)-1);
+
+  reg [WORD:0] data_out_r;
+  reg [WORD:0] memory [0:DEPTH];
+
+  always @(posedge clk) begin
+    if (write_enable) begin
+      memory[address_in_w] <= data_in;
+    end
+    data_out_r <= memory[address_in_r>>1];
+  end
+
+  assign data_out = address_in_r[0] ? data_out_r[WORD:DATA_WIDTH] : data_out_r[DATA_WIDTH-1:0];
+
+endmodule // sync_ram_sdp_wwr
+
+
+module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra=9
+   (input  wire                         clk, write_enable,
+    input  wire  [DATA_WIDTH-1:0]       data_in,
+    input  wire  [ADDRESS_WIDTH-1:0]    address_in_w,
+    input  wire  [ADDRESS_WIDTH-2:0]    address_in_r,
+    output wire  [(DATA_WIDTH*1)-1:0]   data_out);
+
+  localparam WORD  = (DATA_WIDTH-1);
+  localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+  reg [WORD:0] data_out_r0;
+  reg [WORD:0] data_out_r1;
+  reg [WORD:0] memory [0:DEPTH];
+
+  always @(posedge clk) begin
+    if (write_enable)
+      memory[address_in_w] <= data_in;
+    data_out_r0 <= memory[address_in_r<<1+0];
+    data_out_r1 <= memory[address_in_r<<1+1];
+  end
+
+  assign data_out = {data_out_r0, data_out_r1};
+
+endmodule // sync_ram_sdp_wrr
+
+
 module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
    (input  wire                      clk_a, clk_b, 
     input  wire                      write_enable_a, write_enable_b,

tests/arch/quicklogic/qlf_k6n10f/.gitignore

@@ -0,0 +1 @@
+t_*.ys

tests/arch/quicklogic/qlf_k6n10f/gen_memories.py

@@ -0,0 +1,51 @@
+blockram_template = """\
+design -reset; read_verilog -defer ../../common/blockram.v
+chparam -set ADDRESS_WIDTH {aw} -set DATA_WIDTH {dw} {top}
+hierarchy -top {top}
+synth_quicklogic -family qlf_k6n10f -top {top}; cd {top}
+log TESTING aw:{aw} dw:{dw} top:{top}\
+"""
+blockram_tests: "list[tuple[int, int, str, list[str]]]" = [
+    # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work
+    (10, 36, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (11, 18, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (12,  9, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    # larger sizes need an extra ram
+    (10, 48, "sync_ram_*dp",     ["-assert-count 2 t:TDP36K"]),
+    (11, 36, "sync_ram_*dp",     ["-assert-count 2 t:TDP36K"]),
+    (12, 18, "sync_ram_*dp",     ["-assert-count 2 t:TDP36K"]),
+    (12, 10, "sync_ram_*dp",     ["-assert-count 2 t:TDP36K"]),
+    # 4096x20bit *can* fit in 3, albeit somewhat awkwardly
+    (12, 20, "sync_ram_*dp",     ["-assert-min 3 t:TDP36K",
+                                  "-assert-max 4 t:TDP36K"]),
+    # smaller sizes can still fit in one
+    (10, 32, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (10, 18, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (10,  9, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (11, 16, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (11,  9, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (12,  8, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (13,  4, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (14,  2, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    (15,  1, "sync_ram_*dp",     ["-assert-count 1 t:TDP36K"]),
+    # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K)
+    (11, 18, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
+    (11,  9, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]),
+    # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K)
+    (11, 18, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
+    (10, 36, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]),
+]
+
+with open("t_mem.ys", mode="w") as f:
+    for (aw, dw, top, assertions) in blockram_tests:
+        if "*" in top:
+            star_sub = ["s", "t"]
+        else:
+            star_sub = [""]
+        for sub in star_sub:
+            print(
+                blockram_template.format(aw=aw, dw=dw, top=top.replace("*", sub)),
+                file=f
+            )
+            for assertion in assertions:
+                print("select {}\n".format(assertion), file=f, end=None)