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11329 Commits

Author SHA1 Message Date
Claire Xen 19773d093f
Update verific.cc 
Ad-hoc fixes/improvements
 2021-12-10 14:27:18 +01:00
Claire Xen ce82afe44f
Merge pull request #3099 from YosysHQ/claire/readargs 
Use "read" command to parse HDL files from Yosys command-line
 2021-12-10 11:23:53 +01:00
Claire Xenia Wolf d6e4d3f1ba Fix the tests we just broke 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:22:37 +01:00
Claire Xenia Wolf ce08046f44 Added "yosys -r <topmodule>" 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:15:37 +01:00
Claire Xenia Wolf 0cbdb42dcd Use "read" command to parse HDL files from Yosys command-line 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-09 10:33:55 +01:00
github-actions[bot] cdb5711875 Bump version 2021-12-09 00:55:26 +00:00
Marcelina Kościelnicka 1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Miodrag Milanovic b06f547993 If direction NONE use that from first bit 2021-12-08 11:50:10 +01:00
github-actions[bot] d186ea7a2d Bump version 2021-12-04 00:54:12 +00:00
Miodrag Milanovic c23cd00f30 Next dev cycle 2021-12-03 12:51:34 +01:00
Miodrag Milanovic 2156e20db5 Release version 0.12 2021-12-03 12:48:49 +01:00
Miodrag Milanovic 71e762d68c Update manual 2021-12-03 09:57:14 +01:00
Miodrag Milanovic d65942b9ac Add gitignore for gatemate 2021-12-03 09:56:37 +01:00
Miodrag Milanovic 3ebfa3fb84 Make sure cell names are unique for wide operators 2021-12-03 09:49:05 +01:00
github-actions[bot] 2be110cb0b Bump version 2021-12-02 00:54:50 +00:00
Miodrag Milanovic 4792d925fc Update CHANGELOG and CODEOWNERS 2021-12-01 08:42:37 +01:00
github-actions[bot] 707d98b06c Bump version 2021-11-26 00:52:41 +00:00
Lofty a31c8a82be intel_alm: preliminary Arria V support 2021-11-25 17:20:36 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
github-actions[bot] 113c943841 Bump version 2021-11-18 00:54:02 +00:00
Miodrag Milanović d0fda4c0ef
Merge pull request #3080 from YosysHQ/micko/init_wire 
Give initial wire unique ID, fixes #2914
 2021-11-17 13:57:56 +01:00
Miodrag Milanovic c081c683a4 Give initial wire unique ID, fixes #2914 2021-11-17 12:19:06 +01:00
github-actions[bot] 07dde32bf1 Bump version 2021-11-17 00:53:07 +00:00
Kamil Rakoczy fdb19a5b3a
Support parameters using struct as a wiretype (#3050) 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-11-16 10:59:54 +01:00
github-actions[bot] 06bddb5e49 Bump version 2021-11-14 00:54:56 +00:00
Patrick Urban cb41209095 synth_gatemate Revert cascade A/B port mixup 2021-11-13 21:53:25 +01:00
Patrick Urban decdc743db synth_gatemate: Remove iob_map invokation 2021-11-13 21:53:25 +01:00
Patrick Urban 0d871b6c49 synth_gatemate: Add block RAM cascade support 
* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
 2021-11-13 21:53:25 +01:00
Patrick Urban 285ec0547b synth_gatemate: Remove obsolete iob_map 2021-11-13 21:53:25 +01:00
Patrick Urban 81964d6d6f synth_gatemate: Update pass 
* remove `write_edif` and `write_blif` options
* remove redundant `abc` call before muxcover
* update style
 2021-11-13 21:53:25 +01:00
Patrick Urban 74aee88e81 synth_gatemate: Remove specify blocks 2021-11-13 21:53:25 +01:00
Patrick Urban 05f24adca9 synth_gatemate: Remove gatemate_bramopt pass 2021-11-13 21:53:25 +01:00
Patrick Urban 97d03c2b3b synth_gatemate: Apply new test practice with assert-max 2021-11-13 21:53:25 +01:00
Patrick Urban 76bf96d310 synth_gatemate: Fix fsm test 2021-11-13 21:53:25 +01:00
Patrick Urban 4bee908ae8 synth_gatemate: Revise block RAM read modes and initialization 
* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
 2021-11-13 21:53:25 +01:00
Patrick Urban 3f4ccdf2f5 synth_gatemate: Remove unsupported FF initialization 2021-11-13 21:53:25 +01:00
Patrick Urban d592bd93b8 synth_gatemate: Rename multiplier factor parameters 2021-11-13 21:53:25 +01:00
Patrick Urban 6825de6343 synth_gatemate: Registers are uninitialized 2021-11-13 21:53:25 +01:00
Patrick Urban acb993b27b Allow initial blocks to be disabled during tests 
Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
 2021-11-13 21:53:25 +01:00
Patrick Urban 0a72952d5f synth_gatemate: Apply review remarks 
* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
 2021-11-13 21:53:25 +01:00
Patrick Urban cfcc38582a synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
Patrick Urban 240d289fff synth_gatemate: Initial implementation 
Signed-off-by: Patrick Urban <patrick.urban@web.de>
 2021-11-13 21:53:25 +01:00
github-actions[bot] b3e2001e1f Bump version 2021-11-13 00:52:01 +00:00
Marcelina Kościelnicka 107aad2cd2 show: Fix wire bit indexing. 
Fixes #3078.
 2021-11-12 15:09:58 +01:00
Miodrag Milanovic 48a628522b update abc 2021-11-12 12:40:24 +01:00
Miodrag Milanovic b4f68e3cca Update abc 2021-11-12 09:00:32 +01:00
github-actions[bot] 1df8ac58fe Bump version 2021-11-11 00:54:18 +00:00
Claire Xen a6c90c9772
Merge pull request #3075 from YosysHQ/micko/verific_mem_size 
No need to allocate more memory than used
 2021-11-10 20:24:00 +01:00
Claire Xen 4699ddcc1b
Merge pull request #3077 from YosysHQ/claire/genlib 
Add genlib support to ABC command
 2021-11-10 20:02:34 +01:00
Claire Xen c77d5a2aac
Spelling fix in abc.cc 2021-11-10 16:47:54 +01:00