riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

synth_gatemate: Registers are uninitialized

This commit is contained in:
Patrick Urban 2021-09-24 21:52:09 +02:00 committed by Marcelina Kościelnicka
parent acb993b27b
commit 6825de6343
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/gatemate/cells_sim.v
View File

@ -294,7 +294,7 @@ module CC_DFF #(
assign en = (EN_INV) ? ~EN : EN;
assign sr = (SR_INV) ? ~SR : SR;
initial Q = 1'b0;
initial Q = 1'bX;
always @(posedge clk or posedge sr)
begin
@ -323,7 +323,7 @@ module CC_DLT #(
assign en = (G_INV) ? ~G : G;
assign sr = (SR_INV) ? ~SR : SR;
initial Q = 1'b0;
initial Q = 1'bX;
always @(*)
begin

2
techlibs/gatemate/synth_gatemate.cc
View File

@ -305,7 +305,7 @@ struct SynthGateMatePass : public ScriptPass
if (check_label("map_regs"))
{
run("opt_clean");
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_DLATCH_???_ 0");
run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");