mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3099 from YosysHQ/claire/readargs
Use "read" command to parse HDL files from Yosys command-line
This commit is contained in:
Claire Xen
GitHub
commit
ce82afe44f
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@ -118,7 +118,7 @@ int main(int argc, char **argv)
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if (argc == 2)
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{
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// Run the first argument as a script file
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run_frontend(argv[1], "script", 0, 0, 0);
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run_frontend(argv[1], "script");
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}
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}
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@ -202,12 +202,13 @@ int main(int argc, char **argv)
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std::string output_filename = "";
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std::string scriptfile = "";
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std::string depsfile = "";
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std::string topmodule = "";
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bool scriptfile_tcl = false;
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bool got_output_filename = false;
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bool print_banner = true;
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bool print_stats = true;
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bool call_abort = false;
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bool timing_details = false;
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bool run_shell = true;
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bool mode_v = false;
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bool mode_q = false;
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@ -288,6 +289,9 @@ int main(int argc, char **argv)
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printf(" -A\n");
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printf(" will call abort() at the end of the script. for debugging\n");
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printf("\n");
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printf(" -r <module_name>\n");
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printf(" elaborate command line arguments using the specified top module\n");
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printf("\n");
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printf(" -D <macro>[=<value>]\n");
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printf(" set the specified Verilog define (via \"read -define\")\n");
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printf("\n");
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@ -342,7 +346,7 @@ int main(int argc, char **argv)
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}
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int opt;
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while ((opt = getopt(argc, argv, "MXAQTVSgm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:P:E:x:")) != -1)
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while ((opt = getopt(argc, argv, "MXAQTVSgm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:r:D:P:E:x:")) != -1)
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{
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switch (opt)
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{
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@ -384,13 +388,15 @@ int main(int argc, char **argv)
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break;
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case 'b':
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backend_command = optarg;
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run_shell = false;
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break;
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case 'p':
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passes_commands.push_back(optarg);
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run_shell = false;
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break;
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case 'o':
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output_filename = optarg;
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got_output_filename = true;
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run_shell = false;
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break;
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case 'l':
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case 'L':
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@ -422,10 +428,12 @@ int main(int argc, char **argv)
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case 's':
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scriptfile = optarg;
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scriptfile_tcl = false;
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run_shell = false;
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break;
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case 'c':
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scriptfile = optarg;
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scriptfile_tcl = true;
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run_shell = false;
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break;
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case 'W':
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log_warn_regexes.push_back(YS_REGEX_COMPILE(optarg));
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@ -436,6 +444,9 @@ int main(int argc, char **argv)
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case 'e':
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log_werror_regexes.push_back(YS_REGEX_COMPILE(optarg));
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break;
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case 'r':
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topmodule = optarg;
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break;
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case 'D':
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vlog_defines.push_back(optarg);
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break;
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@ -506,12 +517,6 @@ int main(int argc, char **argv)
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for (auto &fn : plugin_filenames)
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load_plugin(fn, {});
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if (optind == argc && passes_commands.size() == 0 && scriptfile.empty()) {
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if (!got_output_filename)
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backend_command = "";
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shell(yosys_design);
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}
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if (!vlog_defines.empty()) {
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std::string vdef_cmd = "read -define";
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for (auto vdef : vlog_defines)
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@ -520,7 +525,11 @@ int main(int argc, char **argv)
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}
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while (optind < argc)
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run_frontend(argv[optind++], frontend_command, output_filename == "-" ? &backend_command : NULL);
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if (run_frontend(argv[optind++], frontend_command))
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run_shell = false;
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if (!topmodule.empty())
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run_pass("hierarchy -top " + topmodule);
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if (!scriptfile.empty()) {
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if (scriptfile_tcl) {
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@ -531,13 +540,15 @@ int main(int argc, char **argv)
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log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n");
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#endif
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} else
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run_frontend(scriptfile, "script", output_filename == "-" ? &backend_command : NULL);
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run_frontend(scriptfile, "script");
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}
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for (auto it = passes_commands.begin(); it != passes_commands.end(); it++)
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run_pass(*it);
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if (!backend_command.empty())
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if (run_shell)
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shell(yosys_design);
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else
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run_backend(output_filename, backend_command);
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yosys_design->check();
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@ -956,7 +956,7 @@ static void handle_label(std::string &command, bool &from_to_active, const std::
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}
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}
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void run_frontend(std::string filename, std::string command, std::string *backend_command, std::string *from_to_label, RTLIL::Design *design)
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bool run_frontend(std::string filename, std::string command, RTLIL::Design *design, std::string *from_to_label)
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{
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if (design == nullptr)
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design = yosys_design;
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@ -966,11 +966,11 @@ void run_frontend(std::string filename, std::string command, std::string *backen
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if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0)
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filename_trim.erase(filename_trim.size()-3);
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if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0)
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command = "verilog";
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command = " -vlog2k";
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else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0)
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command = "verilog -sv";
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command = " -sv";
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else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
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command = "vhdl";
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command = " -vhdl";
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else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0)
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command = "blif";
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else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0)
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@ -1056,10 +1056,12 @@ void run_frontend(std::string filename, std::string command, std::string *backen
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if (filename != "-")
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fclose(f);
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if (backend_command != NULL && *backend_command == "auto")
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*backend_command = "";
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return true;
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}
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return;
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if (command == "tcl") {
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Pass::call(design, vector<string>({command, filename}));
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return true;
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}
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if (filename == "-") {
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@ -1068,16 +1070,15 @@ void run_frontend(std::string filename, std::string command, std::string *backen
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log("\n-- Parsing `%s' using frontend `%s' --\n", filename.c_str(), command.c_str());
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}
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if (command == "tcl")
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Pass::call(design, vector<string>({command, filename}));
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else
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if (command[0] == ' ') {
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auto argv = split_tokens("read" + command);
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argv.push_back(filename);
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Pass::call(design, argv);
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} else
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Frontend::frontend_call(design, NULL, filename, command);
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design->check();
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}
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void run_frontend(std::string filename, std::string command, RTLIL::Design *design)
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{
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run_frontend(filename, command, nullptr, nullptr, design);
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design->check();
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return false;
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}
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void run_pass(std::string command, RTLIL::Design *design)
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@ -1391,7 +1392,7 @@ struct ScriptCmdPass : public Pass {
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else if (args.size() == 2)
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run_frontend(args[1], "script", design);
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else if (args.size() == 3)
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run_frontend(args[1], "script", NULL, &args[2], design);
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run_frontend(args[1], "script", design, &args[2]);
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else
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extra_args(args, 2, design, false);
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}
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@ -347,8 +347,7 @@ std::vector<std::string> glob_filename(const std::string &filename_pattern);
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void rewrite_filename(std::string &filename);
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void run_pass(std::string command, RTLIL::Design *design = nullptr);
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void run_frontend(std::string filename, std::string command, std::string *backend_command, std::string *from_to_label = nullptr, RTLIL::Design *design = nullptr);
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void run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr);
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bool run_frontend(std::string filename, std::string command, RTLIL::Design *design = nullptr, std::string *from_to_label = nullptr);
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void run_backend(std::string filename, std::string command, RTLIL::Design *design = nullptr);
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void shell(RTLIL::Design *design);
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@ -1,5 +1,5 @@
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! ../../../yosys -qp "synth_xilinx" ../common/tribuf.v
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../../../yosys -qp "synth_xilinx -iopad; \
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../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v
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../../../yosys -f verilog -qp "synth_xilinx -iopad; \
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select -assert-count 2 t:IBUF; \
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select -assert-count 1 t:INV; \
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select -assert-count 1 t:OBUFT" ../common/tribuf.v
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@ -1,6 +1,6 @@
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#!/bin/bash
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set -e
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../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
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../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
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-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
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iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
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temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
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@ -18,7 +18,7 @@ ${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v
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for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
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echo -n "Testing expectations for $f .."
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../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
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../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
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if grep -q expect-wr-ports $f; then
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grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected number of write ports."; false; }
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@ -2,7 +2,7 @@
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set -e
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../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
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../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat'
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iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
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iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v
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@ -1,3 +1,3 @@
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set -e
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../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v
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../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar'
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@ -1,9 +1,9 @@
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#!/bin/bash
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set -ex
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../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v
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../../yosys -q -o async_prp.v -p 'prep; rename uut prp' async.v
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../../yosys -q -o async_a2s.v -p 'prep; async2sync; rename uut a2s' async.v
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../../yosys -q -o async_ffl.v -p 'prep; clk2fflogic; rename uut ffl' async.v
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../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
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../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
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../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
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../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
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iverilog -o async_sim -DTESTBENCH async.v async_???.v
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vvp -N async_sim > async.out
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tail async.out
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