mirror of https://github.com/YosysHQ/yosys.git
synth_gatemate: Add block RAM cascade support
* add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
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285ec0547b
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0d871b6c49
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@ -50,19 +50,13 @@ module \$__CC_BRAM_20K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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wire [15:0] ADDRA = {A1ADDR, 7'b0};
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wire [15:0] ADDRB = {B1ADDR, 7'b0};
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localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
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localparam INIT_CHUNK_SIZE = 320;
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function [319:0] permute_init;
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input [INIT_CHUNK_SIZE-1:0] chunk;
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integer i;
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begin
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if (CFG_DBITS <= 2) begin
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for (i = 0; i < 64; i = i + 1) begin
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permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
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end
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end else begin
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permute_init = chunk;
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end
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permute_init = chunk;
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end
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endfunction
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@ -133,19 +127,13 @@ module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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wire [15:0] ADDRA = {A1ADDR, 7'b0};
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wire [15:0] ADDRB = {B1ADDR, 7'b0};
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localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;
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localparam INIT_CHUNK_SIZE = 320;
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function [319:0] permute_init;
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input [INIT_CHUNK_SIZE-1:0] chunk;
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integer i;
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begin
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if (CFG_DBITS <= 2) begin
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for (i = 0; i < 64; i = i + 1) begin
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permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
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end
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end else begin
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permute_init = chunk;
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end
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permute_init = chunk;
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end
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endfunction
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@ -173,7 +161,7 @@ module \$__CC_BRAM_40K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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.B_ECC_2B_ERR(B_ECC_2B_ERR),
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.A_CLK(CLK2),
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.B_CLK(CLK3),
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.A_EN(|A1EN),
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.A_EN(1'b1),
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.B_EN(B1EN),
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.A_WE(|A1EN),
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.B_WE(1'b0),
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@ -440,7 +428,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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wire A_CAS, B_CAS;
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// unconnected signals
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wire [39:0] A_UP_DO, A_LO_DO, B_LO_DO;
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wire [39:0] A_UP_DO;
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wire A_ECC_1B_ERR, B_ECC_1B_ERR, A_ECC_2B_ERR, B_ECC_2B_ERR;
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localparam INIT_CHUNK_SIZE = 256;
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@ -462,7 +450,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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`undef INIT_UPPER
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.LOC("UNPLACED"),
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.CAS("UPPER"),
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.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
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.A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
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.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
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.RAM_MODE("TDP"),
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.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
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@ -474,8 +462,8 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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) upper_cell (
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.A_CI(A_CAS),
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.B_CI(B_CAS),
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.A_DO(A_UP_DO),
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.B_DO(B1DATA),
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.A_DO(B1DATA),
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.B_DO(A_UP_DO),
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.A_ECC_1B_ERR(A_ECC_1B_ERR),
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.B_ECC_1B_ERR(B_ECC_1B_ERR),
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.A_ECC_2B_ERR(A_ECC_2B_ERR),
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@ -500,7 +488,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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`undef INIT_LOWER
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.LOC("UNPLACED"),
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.CAS("LOWER"),
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.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
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.A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
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.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
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.RAM_MODE("TDP"),
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.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
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@ -510,7 +498,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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.A_DO_REG(1'b0), .B_DO_REG(1'b0),
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.A_ECC_EN(1'b0), .B_ECC_EN(1'b0)
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) lower_cell (
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.A_CI(1'b1),
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.A_CI(),
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.B_CI(),
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.A_CO(A_CAS),
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.B_CO(B_CAS),
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@ -666,41 +666,11 @@ module CC_BRAM_20K (
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generate
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if (RAM_MODE == "SDP") begin
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// Port A (write)
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if (A_WR_WIDTH <= 1) begin
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assign addra = A_ADDR[15:7] + (A_ADDR[15:7]/4);
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end
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else if (A_WR_WIDTH <= 2) begin
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assign addra = A_ADDR[15:7]*2 + (A_ADDR[15:7]/2);
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end
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else if (A_WR_WIDTH <= 5) begin
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assign addra = A_ADDR[15:7]*5;
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end
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else if (A_WR_WIDTH <= 10) begin
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assign addra = A_ADDR[15:7]*10;
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end
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else if (A_WR_WIDTH <= 20) begin
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assign addra = A_ADDR[15:7]*20;
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end
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else if (A_WR_WIDTH <= 40) begin
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if (A_WR_WIDTH == 40) begin
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assign addra = A_ADDR[15:7]*40;
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end
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// Port B (read)
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if (B_RD_WIDTH <= 1) begin
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assign addrb = B_ADDR[15:7] + (B_ADDR[15:7]/4);
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end
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else if (B_RD_WIDTH <= 2) begin
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assign addrb = B_ADDR[15:7]*2 + (B_ADDR[15:7]/2);
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end
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else if (B_RD_WIDTH <= 5) begin
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assign addrb = B_ADDR[15:7]*5;
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end
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else if (B_RD_WIDTH <= 10) begin
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assign addrb = B_ADDR[15:7]*10;
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end
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else if (B_RD_WIDTH <= 20) begin
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assign addrb = B_ADDR[15:7]*20;
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end
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else if (B_RD_WIDTH <= 40) begin
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if (B_RD_WIDTH == 40) begin
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assign addrb = B_ADDR[15:7]*40;
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end
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end
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@ -849,8 +819,8 @@ module CC_BRAM_40K (
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output B_ECC_1B_ERR,
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output A_ECC_2B_ERR,
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output B_ECC_2B_ERR,
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output A_CO,
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output B_CO,
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output reg A_CO = 0,
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output reg B_CO = 0,
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(* clkbuf_sink *)
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input A_CLK,
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(* clkbuf_sink *)
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@ -1065,6 +1035,14 @@ module CC_BRAM_40K (
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$display("ERROR: Port B width of 80 bits is only supported in SDP mode.");
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$finish();
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end
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if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_A > 1)) begin
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$display("ERROR: Port A cascade mode only supported in 1 bit mode.");
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$finish();
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end
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if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_B > 1)) begin
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$display("ERROR: Port B cascade mode only supported in 1 bit mode.");
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$finish();
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end
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if ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&
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(WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin
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$display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A);
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@ -1075,10 +1053,6 @@ module CC_BRAM_40K (
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$display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, WIDTH_MODE_B);
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$finish();
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end
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if (CAS != "NONE") begin
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$display("WARNING: Cascade simulation model not yet supported.");
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$finish();
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end
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if ((CAS != "NONE") && ((WIDTH_MODE_A > 1) || (WIDTH_MODE_B > 1))) begin
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$display("ERROR: Cascade feature only supported in 1 bit data width mode.");
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$finish();
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@ -1235,47 +1209,11 @@ module CC_BRAM_40K (
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generate
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if (RAM_MODE == "SDP") begin
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// Port A (write)
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if (A_WR_WIDTH <= 1) begin
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assign addra = A_ADDR[15:7] + (A_ADDR[15:7]/4);
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end
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else if (A_WR_WIDTH <= 2) begin
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assign addra = A_ADDR[15:7]*2 + (A_ADDR[15:7]/2);
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end
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else if (A_WR_WIDTH <= 5) begin
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assign addra = A_ADDR[15:7]*5;
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end
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else if (A_WR_WIDTH <= 10) begin
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assign addra = A_ADDR[15:7]*10;
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end
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else if (A_WR_WIDTH <= 20) begin
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assign addra = A_ADDR[15:7]*20;
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end
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else if (A_WR_WIDTH <= 40) begin
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assign addra = A_ADDR[15:7]*40;
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end
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else if (A_WR_WIDTH <= 80) begin
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if (A_WR_WIDTH == 80) begin
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assign addra = A_ADDR[15:7]*80;
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end
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// Port B (read)
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if (B_RD_WIDTH <= 1) begin
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assign addrb = B_ADDR[15:7] + (B_ADDR[15:7]/4);
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end
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else if (B_RD_WIDTH <= 2) begin
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assign addrb = B_ADDR[15:7]*2 + (B_ADDR[15:7]/2);
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end
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else if (B_RD_WIDTH <= 5) begin
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assign addrb = B_ADDR[15:7]*5;
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end
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else if (B_RD_WIDTH <= 10) begin
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assign addrb = B_ADDR[15:7]*10;
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end
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else if (B_RD_WIDTH <= 20) begin
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assign addrb = B_ADDR[15:7]*20;
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end
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else if (B_RD_WIDTH <= 40) begin
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assign addrb = B_ADDR[15:7]*40;
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end
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else if (B_RD_WIDTH <= 80) begin
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if (B_RD_WIDTH == 80) begin
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assign addrb = B_ADDR[15:7]*80;
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end
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end
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@ -1354,22 +1292,66 @@ module CC_BRAM_40K (
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end
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end
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else if (RAM_MODE == "TDP") begin
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// {A,B}_ADDR[0]=0 selects lower, {A,B}_ADDR[0]=1 selects upper cascade memory
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wire upper_sel_a = ((CAS == "UPPER") && (A_ADDR[0] == 1));
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wire lower_sel_a = ((CAS == "LOWER") && (A_ADDR[0] == 0));
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wire upper_sel_b = ((CAS == "UPPER") && (B_ADDR[0] == 1));
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wire lower_sel_b = ((CAS == "LOWER") && (B_ADDR[0] == 0));
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reg dumm;
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// Cascade output port A
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always @(*)
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begin
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if ((A_WR_MODE == "NO_CHANGE") && lower_sel_a) begin
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A_CO = memory[addra];
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end
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else if ((A_WR_MODE == "WRITE_THROUGH") && lower_sel_a) begin
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A_CO = ((wea && A_BM[0]) ? (A_DI[0]) : (memory[addra]));
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end
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end
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// Cascade output port B
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always @(*)
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begin
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if ((B_WR_MODE == "NO_CHANGE") && lower_sel_b) begin
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B_CO = memory[addrb];
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end
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else if ((B_WR_MODE == "WRITE_THROUGH") && lower_sel_b) begin
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B_CO = ((web && B_BM[0]) ? (B_DI[0]) : (memory[addrb]));
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end
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end
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// TDP port A
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always @(posedge clka)
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begin
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for (i=0; i < WIDTH_MODE_A; i=i+1) begin
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if (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i];
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if (upper_sel_a || lower_sel_a || (CAS == "NONE")) begin
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if (ena && wea && A_BM[i])
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memory[addra+i] <= A_DI[i];
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end
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if (A_WR_MODE == "NO_CHANGE") begin
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if (ena && !wea) A_DO_out[i] <= memory[addra+i];
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if (ena && !wea) begin
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if (CAS == "UPPER") begin
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A_DO_out[i] <= ((A_ADDR[0] == 1) ? (memory[addra+i]) : (A_CI));
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end
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else if (CAS == "NONE") begin
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A_DO_out[i] <= memory[addra+i];
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end
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end
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end
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else if (A_WR_MODE == "WRITE_THROUGH") begin
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if (ena) begin
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if (wea && A_BM[i]) begin
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A_DO_out[i] <= A_DI[i];
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if (CAS == "UPPER") begin
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if (A_ADDR[0] == 1) begin
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A_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));
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end else begin
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A_DO_out[i] <= A_CI;
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end
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end
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else begin
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A_DO_out[i] <= memory[addra+i];
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else if (CAS == "NONE") begin
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A_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i]));
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end
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end
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end
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@ -1379,18 +1361,32 @@ module CC_BRAM_40K (
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always @(posedge clkb)
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begin
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for (i=0; i < WIDTH_MODE_B; i=i+1) begin
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if (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i];
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if (upper_sel_b || lower_sel_b || (CAS == "NONE")) begin
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if (enb && web && B_BM[i])
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memory[addrb+i] <= B_DI[i];
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end
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if (B_WR_MODE == "NO_CHANGE") begin
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if (enb && !web) B_DO_out[i] <= memory[addrb+i];
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if (enb && !web) begin
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if (CAS == "UPPER") begin
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B_DO_out[i] <= ((B_ADDR[0] == 1) ? (memory[addrb+i]) : (B_CI));
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end
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else if (CAS == "NONE") begin
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B_DO_out[i] <= memory[addrb+i];
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end
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end
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end
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else if (B_WR_MODE == "WRITE_THROUGH") begin
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if (enb) begin
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if (web && B_BM[i]) begin
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B_DO_out[i] <= B_DI[i];
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if (CAS == "UPPER") begin
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if (B_ADDR[0] == 1) begin
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B_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));
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end else begin
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B_DO_out[i] <= B_CI;
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end
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end
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else begin
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B_DO_out[i] <= memory[addrb+i];
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else if (CAS == "NONE") begin
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B_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i]));
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end
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end
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end
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@ -1419,5 +1415,5 @@ module CC_BRAM_40K (
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else begin
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assign B_DO = B_DO_out;
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end
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endgenerate
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endgenerate
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endmodule
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