Clifford Wolf
c3cc9839a9
Added port swapping and compatible types to "extract" pass
2013-02-28 10:00:42 +01:00
Clifford Wolf
08c43f27af
Added "extract -constports" feature
2013-02-27 23:39:10 +01:00
Clifford Wolf
a6cf02bdc7
Changed default frontend for "-" to "script" (was: "ilang")
2013-02-27 23:38:38 +01:00
Clifford Wolf
500786af55
Fixed "extract" pass for non-optimized needles
2013-02-27 23:19:30 +01:00
Clifford Wolf
1bbc2b34c8
Added support for simple gates with one constant input to opt_const
2013-02-27 18:00:01 +01:00
Clifford Wolf
da3d55a29c
Added extract -verbose and -map ilang support
2013-02-27 17:26:32 +01:00
Clifford Wolf
f28b6aff40
Implemented basic functionality of "extract" pass
2013-02-27 16:27:20 +01:00
Clifford Wolf
c59d77aa30
Added support for constant signals in "extract" pass
2013-02-27 13:35:30 +01:00
Clifford Wolf
b02e140030
Added "extract" pass (not functional yet)
2013-02-27 13:25:18 +01:00
Clifford Wolf
99d73fe028
Added some additional TODO items
2013-02-27 10:36:17 +01:00
Clifford Wolf
a77a5136af
Fixed typo in README
2013-02-27 09:45:09 +01:00
Clifford Wolf
aa7daadc0a
Added copyright statement to readme file
2013-02-27 09:41:04 +01:00
Clifford Wolf
a321a5c412
Moved stand-alone libs to libs/ directory and added libs/subcircuit
2013-02-27 09:32:19 +01:00
Clifford Wolf
4f0c2862a0
Added support for verilog genblock[index].member syntax
2013-02-26 13:18:22 +01:00
Clifford Wolf
26a192b8c7
Merge pull request #2 from mschmoelzer/master
...
"fsm_export" pass: fix KISS file generation.
2013-02-24 00:08:07 -08:00
Martin Schmölzer
5a005cefe2
"fsm_export" pass: fix KISS file generation.
...
The KISS file format now follows the conventions specified in
"Logic Synthesis and Optimization Benchmarks User Guide", Version 3.0
by Saeyang Yang.
This change ensures interoperability with the "trfsmgen" program by Johann
Glaser.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-02-23 18:22:19 +01:00
Clifford Wolf
6d1502b948
Added support for "always @(*)"
2013-01-16 17:32:11 +01:00
Clifford Wolf
e8231ee46b
Merge pull request #1 from mschmoelzer/master
...
Add support for "fsm_export" synthesis attributes to fsm_export pass
2013-01-08 02:20:24 -08:00
Martin Schmölzer
94502c39a7
Merge remote-tracking branch 'upstream/master'
2013-01-08 09:53:40 +01:00
Martin Schmölzer
4f6cda502d
Add support for "fsm_export" synthesis attributes to fsm_export pass.
...
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.
Verilog example:
(* fsm_export="my_fsm.kiss2" *)
reg [3:0] state;
The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-01-08 09:43:35 +01:00
Clifford Wolf
a24086d1db
Added "getting started" section to README
2013-01-06 14:40:15 +01:00
Clifford Wolf
ae731369dd
Improvements in command shell
...
- Added 'shell' command (run interactive shell from synth script)
- Added support for ; as cmd seperator as in "proc; opt"
- Fixed c++ static initialization order problem with pass register
2013-01-06 13:50:30 +01:00
Clifford Wolf
bc630ba0fa
Added a:*=* syntax to select framework
2013-01-05 12:27:59 +01:00
Clifford Wolf
e9fffd68e3
Added qtcreator.creator.user to top level .gitignore
2013-01-05 12:27:18 +01:00
Clifford Wolf
a7988c01af
Copy attributes from state signal to fsm cell
2013-01-05 11:44:47 +01:00
Clifford Wolf
9c955c4c17
More .gitignore and fixed "make mrproper"
2013-01-05 11:44:29 +01:00
Clifford Wolf
2d9cbd3b02
added more .gitignore files (make test)
2013-01-05 11:35:52 +01:00
Clifford Wolf
6543917fb8
added .gitignore files
2013-01-05 11:19:11 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00