mirror of https://github.com/YosysHQ/yosys.git
Update manual
This commit is contained in:
Miodrag Milanovic
parent
d65942b9ac
commit
71e762d68c
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@ -22,11 +22,11 @@ library to a target architecture.
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if no -script parameter is given, the following scripts are used:
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for -liberty without -constr:
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for -liberty/-genlib without -constr:
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strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
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&nf {D}; &put
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for -liberty with -constr:
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for -liberty/-genlib with -constr:
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strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
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&nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p
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@ -49,10 +49,10 @@ library to a target architecture.
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use different default scripts that are slightly faster (at the cost
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of output quality):
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for -liberty without -constr:
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for -liberty/-genlib without -constr:
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strash; dretime; map {D}
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for -liberty with -constr:
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for -liberty/-genlib with -constr:
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strash; dretime; map {D}; buffer; upsize {D}; dnsize {D};
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stime -p
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@ -69,8 +69,13 @@ library to a target architecture.
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generate netlists for the specified cell library (using the liberty
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file format).
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-genlib <file>
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generate netlists for the specified cell library (using the SIS Genlib
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file format).
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-constr <file>
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pass this file with timing constraints to ABC. use with -liberty.
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pass this file with timing constraints to ABC.
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use with -liberty/-genlib.
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a constr file contains two lines:
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set_driving_cell <cell_name>
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@ -167,7 +172,7 @@ library to a target architecture.
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preserve naming by an equivalence check between the original and post-ABC
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netlists (experimental).
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When neither -liberty nor -lut is used, the Yosys standard cell library is
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When no target cell library is specified the Yosys standard cell library is
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loaded into ABC before the ABC script is executed.
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Note that this is a logic optimization pass within Yosys that is calling ABC
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@ -2402,26 +2407,28 @@ Map module inputs/outputs to PAD cells from a library. This pass
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can only map to very simple PAD cells. Use 'techmap' to further map
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the resulting cells to more sophisticated PAD cells.
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-inpad <celltype> <portname>[:<portname>]
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-inpad <celltype> <in_port>[:<ext_port>]
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Map module input ports to the given cell type with the
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given output port name. if a 2nd portname is given, the
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signal is passed through the pad call, using the 2nd
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portname as the port facing the module port.
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-outpad <celltype> <portname>[:<portname>]
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-inoutpad <celltype> <portname>[:<portname>]
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-outpad <celltype> <out_port>[:<ext_port>]
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-inoutpad <celltype> <io_port>[:<ext_port>]
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Similar to -inpad, but for output and inout ports.
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-toutpad <celltype> <portname>:<portname>[:<portname>]
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-toutpad <celltype> <oe_port>:<out_port>[:<ext_port>]
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Merges $_TBUF_ cells into the output pad cell. This takes precedence
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over the other -outpad cell. The first portname is the enable input
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of the tristate driver.
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of the tristate driver, which can be prefixed with `~` for negative
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polarity enable.
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-tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]
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-tinoutpad <celltype> <oe_port>:<in_port>:<out_port>[:<ext_port>]
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Merges $_TBUF_ cells into the inout pad cell. This takes precedence
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over the other -inoutpad cell. The first portname is the enable input
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of the tristate driver and the 2nd portname is the internal output
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buffering the external signal.
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buffering the external signal. Like with `-toutpad`, the enable can
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be marked as negative polarity by prefixing the name with `~`.
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-ignore <celltype> <portname>[:<portname>]*
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Skips mapping inputs/outputs that are already connected to given
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@ -3156,7 +3163,7 @@ for removal of the read port.
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opt_mem_priority [selection]
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This pass detects cases where one memory write port has priority over another
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even though they can never collide with each other -- ie. there can never be
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even though they can never collide with each other — ie. there can never be
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a situation where a given memory bit is written by both ports at the same
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time, for example because of always-different addresses, or mutually exclusive
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enable signals. In such cases, the priority relation is removed.
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@ -4705,7 +4712,7 @@ to a graphics file (usually SVG or PostScript).
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(including inout ports) are on the right side.
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-pause
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wait for the use to press enter to before returning
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wait for the user to press enter to before returning
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-enum
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enumerate objects with internal ($-prefixed) names
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@ -4907,6 +4914,15 @@ This command splits multi-bit nets into single-bit nets.
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and split nets so that no driver drives only part of a net.
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\end{lstlisting}
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\section{sta -- perform static timing analysis}
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\label{cmd:sta}
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\begin{lstlisting}[numbers=left,frame=single]
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sta [options] [selection]
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This command performs static timing analysis on the design. (Only considers
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paths within a single module, so the design must be flattened.)
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\end{lstlisting}
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\section{stat -- print some statistics}
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\label{cmd:stat}
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\begin{lstlisting}[numbers=left,frame=single]
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@ -5639,6 +5655,149 @@ The following commands are executed by this synthesis command:
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write_json <file-name>
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\end{lstlisting}
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\section{synth\_gatemate -- synthesis for Cologne Chip GateMate FPGAs}
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\label{cmd:synth_gatemate}
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\begin{lstlisting}[numbers=left,frame=single]
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synth_gatemate [options]
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This command runs synthesis for Cologne Chip AG GateMate FPGAs.
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-top <module>
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use the specified module as top module.
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-vlog <file>
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write the design to the specified verilog file. Writing of an output
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file is omitted if this parameter is not specified.
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-json <file>
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write the design to the specified JSON file. Writing of an output file
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is omitted if this parameter is not specified.
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-run <from_label>:<to_label>
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only run the commands between the labels (see below). An empty
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from label is synonymous to 'begin', and empty to label is
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synonymous to the end of the command list.
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-noflatten
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do not flatten design before synthesis.
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-nobram
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do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.
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-noaddf
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do not use CC_ADDF full adder cells in output netlist.
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-nomult
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do not use CC_MULT multiplier cells in output netlist.
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-nomx8, -nomx4
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do not use CC_MX{8,4} multiplexer cells in output netlist.
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-dff
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run 'abc' with -dff option
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-retime
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run 'abc' with '-dff -D 1' options
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-noiopad
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disable I/O buffer insertion (useful for hierarchical or
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out-of-context flows).
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-noclkbuf
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disable automatic clock buffer insertion.
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The following commands are executed by this synthesis command:
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begin:
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read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v
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hierarchy -check -top <top>
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prepare:
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proc
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flatten
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tribuf -logic
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deminout
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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fsm
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opt
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wreduce
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peepopt
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opt_clean
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muxpack
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share
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techmap -map +/cmp2lut.v -D LUT_WIDTH=4
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opt_expr
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opt_clean
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map_mult: (skip if '-nomult')
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techmap -map +/gatemate/mul_map.v
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coarse:
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alumacc
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opt
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memory -nomap
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opt_clean
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map_bram: (skip if '-nobram')
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memory_bram -rules +/gatemate/brams.txt
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setundef -zero -params t:$__CC_BRAM_CASCADE t:$__CC_BRAM_40K_SDP t:$__CC_BRAM_20K_SDP t:$__CC_BRAM_20K_TDP t:$__CC_BRAM_40K_TDP
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techmap -map +/gatemate/brams_map.v
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map_ffram:
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opt -fast -mux_undef -undriven -fine
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memory_map
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opt -undriven -fine
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map_gates:
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techmap -map +/techmap.v -map +/gatemate/arith_map.v
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opt -fast
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map_io: (skip if '-noiopad')
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iopadmap -bits -inpad CC_IBUF Y:I -outpad CC_OBUF A:O -toutpad CC_TOBUF ~T:A:O -tinoutpad CC_IOBUF ~T:Y:A:IO
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clean
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map_regs:
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opt_clean
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dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x
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techmap -map +/gatemate/reg_map.v
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opt_expr -mux_undef
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simplemap
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opt_clean
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map_muxs:
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muxcover -mux4 -mux8
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opt -full
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techmap -map +/gatemate/mux_map.v
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map_luts:
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abc -dress -lut 4
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clean
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map_cells:
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techmap -map +/gatemate/lut_map.v
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clean
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map_bufg: (skip if '-noclkbuf')
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clkbufmap -buf CC_BUFG O:I
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clean
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check:
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hierarchy -check
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stat -width
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check -noinit
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blackbox =A:whitebox
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vlog:
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opt_clean -purge
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write_verilog -noattr <file-name>
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json:
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write_json <file-name>
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\end{lstlisting}
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\section{synth\_gowin -- synthesis for Gowin FPGAs}
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\label{cmd:synth_gowin}
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\begin{lstlisting}[numbers=left,frame=single]
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@ -5724,8 +5883,7 @@ The following commands are executed by this synthesis command:
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techmap -map +/techmap.v -map +/gowin/arith_map.v
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opt -fast
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abc -dff -D 1 (only if -retime)
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splitnets
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iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad $__GW_TBUF OE:I:O -tinoutpad $__GW_IOBUF OE:O:I:IO (unless -noiopads)
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iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO (unless -noiopads)
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map_ffs:
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opt_clean
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@ -5743,6 +5901,7 @@ The following commands are executed by this synthesis command:
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opt_lut_ins -tech gowin
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setundef -undriven -params -zero
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hilomap -singleton -hicell VCC V -locell GND G
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splitnets -ports (only if -vout used)
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clean
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autoname
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@ -5753,7 +5912,7 @@ The following commands are executed by this synthesis command:
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blackbox =A:whitebox
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vout:
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write_verilog -decimal -attr2comment -defparam -renameprefix gen <file-name>
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write_verilog -simple-lhs -decimal -attr2comment -defparam -renameprefix gen <file-name>
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write_json <file-name>
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\end{lstlisting}
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@ -6138,7 +6297,7 @@ This command runs synthesis for ALM-based Intel FPGAs.
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-family <family>
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target one of:
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"cyclonev" - Cyclone V (default)
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"cyclone10gx" - Cyclone 10GX
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"arriav" - Arria V (non-GZ) "cyclone10gx" - Cyclone 10GX
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-vqm <file>
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write the design to the specified Verilog Quartus Mapping File. Writing of an
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@ -6316,7 +6475,7 @@ The following commands are executed by this synthesis command:
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opt -fast
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map_ios: (unless -noiopad)
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iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD OE:I:O -tinoutpad $__FACADE_TINOUTPAD OE:O:I:B A:top
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iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD ~T:I:O -tinoutpad $__FACADE_TINOUTPAD ~T:O:I:B A:top
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attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]
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attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]
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@ -6466,7 +6625,7 @@ The following commands are executed by this synthesis command:
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map_gates:
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techmap -map +/techmap.v -map +/nexus/arith_map.v
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iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad $__NX_TOUTPAD OE:I:O -tinoutpad $__NX_TINOUTPAD OE:O:I:B A:top (skip if '-noiopad')
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iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top (skip if '-noiopad')
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opt -fast
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abc -dff -D 1 (only if -retime)
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@ -6876,7 +7035,7 @@ The following commands are executed by this synthesis command:
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opt -fast
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map_cells:
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iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top (skip if '-noiopad')
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iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top (skip if '-noiopad')
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techmap -map +/techmap.v -map +/xilinx/cells_map.v
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clean
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