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synth_gatemate Revert cascade A/B port mixup

This commit is contained in:
Patrick Urban 2021-11-12 08:47:15 +01:00 committed by Marcelina Kościelnicka
parent decdc743db
commit cb41209095
2 changed files with 4 additions and 12 deletions
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8
techlibs/gatemate/brams_map.v
View File

@ -450,7 +450,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
`undef INIT_UPPER
.LOC("UNPLACED"),
.CAS("UPPER"),
.A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
@ -462,8 +462,8 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
) upper_cell (
.A_CI(A_CAS),
.B_CI(B_CAS),
.A_DO(B1DATA),
.B_DO(A_UP_DO),
.A_DO(A_UP_DO),
.B_DO(B1DATA),
.A_ECC_1B_ERR(A_ECC_1B_ERR),
.B_ECC_1B_ERR(B_ECC_1B_ERR),
.A_ECC_2B_ERR(A_ECC_2B_ERR),
@ -488,7 +488,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
`undef INIT_LOWER
.LOC("UNPLACED"),
.CAS("LOWER"),
.A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
.RAM_MODE("TDP"),
.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),

8
techlibs/gatemate/cells_sim.v
View File

@ -1035,14 +1035,6 @@ module CC_BRAM_40K (
$display("ERROR: Port B width of 80 bits is only supported in SDP mode.");
$finish();
end
if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_A > 1)) begin
$display("ERROR: Port A cascade mode only supported in 1 bit mode.");
$finish();
end
if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_B > 1)) begin
$display("ERROR: Port B cascade mode only supported in 1 bit mode.");
$finish();
end
if ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&
(WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin
$display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A);