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synth_gatemate Revert cascade A/B port mixup
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@ -450,7 +450,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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`undef INIT_UPPER
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.LOC("UNPLACED"),
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.CAS("UPPER"),
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.A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
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.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
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.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
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.RAM_MODE("TDP"),
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.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
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@ -462,8 +462,8 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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) upper_cell (
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.A_CI(A_CAS),
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.B_CI(B_CAS),
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.A_DO(B1DATA),
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.B_DO(A_UP_DO),
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.A_DO(A_UP_DO),
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.B_DO(B1DATA),
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.A_ECC_1B_ERR(A_ECC_1B_ERR),
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.B_ECC_1B_ERR(B_ECC_1B_ERR),
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.A_ECC_2B_ERR(A_ECC_2B_ERR),
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@ -488,7 +488,7 @@ module \$__CC_BRAM_CASCADE (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1
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`undef INIT_LOWER
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.LOC("UNPLACED"),
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.CAS("LOWER"),
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.A_RD_WIDTH(CFG_DBITS), .B_RD_WIDTH(0),
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.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
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.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
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.RAM_MODE("TDP"),
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.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
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@ -1035,14 +1035,6 @@ module CC_BRAM_40K (
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$display("ERROR: Port B width of 80 bits is only supported in SDP mode.");
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$finish();
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end
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if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_A > 1)) begin
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$display("ERROR: Port A cascade mode only supported in 1 bit mode.");
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$finish();
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end
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if (((CAS == "UPPER") || (CAS == "LOWER")) && (WIDTH_MODE_B > 1)) begin
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$display("ERROR: Port B cascade mode only supported in 1 bit mode.");
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$finish();
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end
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if ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) &&
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(WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin
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$display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A);
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