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3884 Commits

Author SHA1 Message Date
Benedikt Tutzer 416946a16a Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more 2018-08-01 10:57:57 +02:00
Benedikt Tutzer 79d7e608cf Setup is called automatically when the module is loaded, shutdown when python exits 2018-08-01 10:57:46 +02:00
Benedikt Tutzer 57d2197703 Cleaned up comments 2018-08-01 10:57:41 +02:00
Benedikt Tutzer b57dafce68 removed unused library and already present compiler flag 2018-08-01 10:57:33 +02:00
Benedikt Tutzer 0371519c39 Added Monitor class that can monitor all changes in a Design or in a Module 2018-07-10 12:51:02 +02:00
Benedikt Tutzer e7d3f3cd46 added destructors for wires and cells 2018-07-10 08:52:36 +02:00
Benedikt Tutzer 55df7fff19 removed debug output 2018-07-09 16:02:10 +02:00
Benedikt Tutzer da8083dbd0 commands can now be run on arbitrary designs, not only on the active one 2018-07-09 16:01:56 +02:00
Benedikt Tutzer 8ebaeecd83 multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues 2018-07-09 15:48:06 +02:00
Benedikt Tutzer 7911379d4a Introduced namespace and removed class-prefixes to increase readability 2018-06-28 15:07:21 +02:00
Benedikt Tutzer ccb4dcd013 changed references from hash-ids to IdString names 2018-06-28 14:44:28 +02:00
Benedikt Tutzer a27fa1833e added wrappers for Design, Modules, Cells and Wires 2018-06-25 17:08:29 +02:00
Benedikt Tutzer 4d4117c998 added ENABLE_PYTHON option in build environment 2018-06-22 11:15:03 +02:00
Clifford Wolf d412b17259 Add simplified "read" command, enable extnets in implicit Verific import 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-21 16:56:55 +02:00
Clifford Wolf 9e096b1512 Merge branch 'master' of github.com:YosysHQ/yosys 2018-06-20 23:45:26 +02:00
Clifford Wolf 5f2bc1ce76 Add automatic verific import in hierarchy command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-20 23:45:01 +02:00
Clifford Wolf c1d6934663
Merge pull request #572 from q3k/q3k/fix-protobuf-build 
Fix protobuf build
 2018-06-20 20:40:59 +02:00
Sergiusz Bazanski 1690dafde1 Fix protobuf build 2018-06-20 19:28:43 +01:00
Clifford Wolf 626b555244
Merge pull request #571 from q3k/q3k/protobuf-backend 
Add Protobuf backend
 2018-06-19 15:02:04 +02:00
Serge Bazanski 53e9a1549c Add Protobuf backend 
Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
 2018-06-19 13:34:56 +01:00
Clifford Wolf 675a44b41a Be slightly less aggressive in "deminout" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-19 14:29:38 +02:00
Clifford Wolf 25c5002f83
Merge pull request #570 from edcote/patch-4 
Include module name for area summary stats
 2018-06-19 13:47:39 +02:00
Edmond Cote d89560a0ba
Include module name for area summary stats 
The PR prints the name of the module when displaying the final area count.

Pros:
- Easier for the user to `grep` for area information about a specific module

Cons:
- Arguably more verbose, less "pretty" than author desires

Verification:
~~~~
30c30
<    Chip area for this module: 20616.349000
---
>    Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
<    Chip area for this module: 88.697700
---
>    Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
<    Chip area for this module: 20705.046700
---
>    Chip area for top module '\picorv32_axi': 20705.046700
~~~~
 2018-06-18 17:29:01 -07:00
Clifford Wolf 0ff0ce4973 Bugfix in liberty parser (as suggested by aiju in #569) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-15 18:56:44 +02:00
Clifford Wolf 57fc8dd582 Add "synth_ice40 -json" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-13 13:35:10 +02:00
Clifford Wolf 83631555dd Fix ice40_opt for cases where a port is connected to a signal with width != 1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-11 18:12:42 +02:00
Clifford Wolf 270c1814b5
Merge pull request #561 from udif/pr_skip_typo 
Fixed typo (sikp -> skip)
 2018-06-06 11:57:41 +02:00
Udi Finkelstein 106af19b69 Fixed typo (sikp -> skip) 2018-06-05 22:41:27 +03:00
Clifford Wolf 4372cf690d Add (* gclk *) attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 13:25:42 +02:00
Clifford Wolf f273291dfe Add setundef -anyseq / -anyconst support to -undriven mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:57:28 +02:00
Clifford Wolf 4cd6d5556a Add "setundef -anyconst" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:49:58 +02:00
Clifford Wolf 3ab79a231b Bugfix in handling of array instances with empty ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-31 18:09:31 +02:00
Clifford Wolf 7f0548c16f Update examples/cmos/counter.ys to use "synth" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 14:17:36 +02:00
Clifford Wolf 7fecc3c199 Make -nordff the default in "prep" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 13:17:09 +02:00
Clifford Wolf a77e27ab15 Update ABC to git rev 6df1396 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 13:10:10 +02:00
Clifford Wolf cee4b1e6bc Disable memory_dff for initialized FFs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 17:16:15 +02:00
Clifford Wolf 74efafc1cf Add some cleanup code to memory_nordff 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 16:42:06 +02:00
Clifford Wolf 9a946c207f Add comment to VIPER #13453 work-around 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 13:36:35 +02:00
Clifford Wolf 001c9f1d45 Fix Verific handling of single-bit anyseq/anyconst wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 15:41:45 +02:00
Clifford Wolf 251562a491 Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 18:13:38 +02:00
Clifford Wolf 4d645f0fce Fix verific handling of anyconst/anyseq attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 17:07:06 +02:00
Clifford Wolf a5f4b44745
Merge pull request #454 from rqou/emscripten-and-abc 
Add option to statically link abc; emscripten fixes
 2018-05-19 08:42:45 +02:00
Robert Ou bea71e71ca Force abc to align memory to 8 bytes 
Apparently abc has a memory pool implementation that by default returns
memory that is unaligned. There is a workaround in the abc makefile that
uses uname to look for "arm" specifically and then sets the alignment.
However, ARM is not the only platform that requires proper alignment
(e.g. emscripten does too). For now, pessimistically force the alignment
for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten
despite being approximately a 32-bit platform).
 2018-05-18 22:53:52 -07:00
Robert Ou 0abe7c6c77 Modify emscripten main to mount nodefs and to run arg as a script 2018-05-18 22:53:52 -07:00
Robert Ou d9ef793430 Force abc to be linked statically and without threads in emscripten 2018-05-18 22:53:47 -07:00
Robert Ou 9763e4d830 Fix infinite loop in abc command under emscripten 2018-05-18 22:42:39 -07:00
Robert Ou bd87462b47 Fix reading techlibs under emscripten 2018-05-18 22:42:33 -07:00
Robert Ou 93f79299a5 Add options to disable abc's usage of pthreads and readline 2018-05-18 22:42:24 -07:00
Robert Ou bfce3a7479 Add an option to statically link abc into yosys 
This is currently incomplete because the output filter no longer works.
 2018-05-18 22:35:28 -07:00
Robert Ou 1b210dbfb7 Makefile: Make abc always use stdint.h 2018-05-18 22:26:29 -07:00