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592 Commits

Author SHA1 Message Date
Clifford Wolf 34005348b6 Bugfix in verilog_defaults argument parser 2017-12-24 17:21:37 +01:00
Clifford Wolf ba90e08398 Add support for Verific PRIM_SVA_NOT properties 2017-12-10 01:10:03 +01:00
Clifford Wolf e4a4c0e10c Add Verific OPER_SVA_STABLE support 2017-12-10 00:59:44 +01:00
Clifford Wolf 27916105a9 Refactoring Verific SVA rewriter 2017-12-10 00:26:26 +01:00
Clifford Wolf 8364f509e3 Fix error handling for nested always/initial 2017-12-02 18:52:05 +01:00
Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00
Clifford Wolf 5b6e52118c Accept real-valued delay values 2017-11-18 10:01:30 +01:00
William D. Jones abc5b4b8ce Accommodate Windows-style paths during include-file processing. 2017-11-14 16:16:24 -05:00
Clifford Wolf a8cf431d9c Remove vhdl2verilog 2017-10-25 14:50:22 +02:00
Clifford Wolf 0a31a0b3ae Remove all PSL support code from verific.cc 2017-10-20 13:14:04 +02:00
Clifford Wolf 1954c78ea7 Add "verific -vlog-libdir" 2017-10-13 20:23:19 +02:00
Clifford Wolf e7a3c47cc7 Add "verific -vlog-incdir" and "verific -vlog-define" 2017-10-13 20:12:51 +02:00
Clifford Wolf 05068af880 Update Verific README 2017-10-13 17:11:53 +02:00
Clifford Wolf bc5cc4e103 Add Verific fairness/liveness support 2017-10-12 12:00:09 +02:00
Clifford Wolf 12c10892e6 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-10-10 15:16:45 +02:00
Clifford Wolf c10e96c9ec Start work on pre-processor for Verific SVA properties 2017-10-10 15:16:39 +02:00
Clifford Wolf bc80426d45 Remove some dead code 2017-10-10 12:00:48 +02:00
Clifford Wolf caa78388cd Allow $past, $stable, $rose, $fell in $global_clock blocks 2017-10-10 11:59:32 +02:00
Clifford Wolf fc3378916d Improve handling of Verific errors 2017-10-05 14:38:32 +02:00
Clifford Wolf ee56a887b6 Improve Verific error handling, check VHDL static asserts 2017-10-04 18:56:28 +02:00
Clifford Wolf b92ff2706e Fix nasty bug in Verific bindings 2017-10-04 17:23:42 +02:00
Clifford Wolf a381188b92 Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys 2017-10-03 18:23:45 +02:00
Udi Finkelstein eb40278a16 Turned a few member functions into const, esp. dumpAst(), dumpVlog(). 2017-09-30 07:37:38 +03:00
Udi Finkelstein 72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution 
(Oreilly 'Flex & Bison' page 189)
 2017-09-30 06:39:07 +03:00
Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Udi Finkelstein e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00
Udi Finkelstein 6ddc6a7af4 $size() seems to work now with or without the optional parameter. 
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
 2017-09-26 19:18:25 +03:00
Udi Finkelstein 7e391ba904 enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog 2017-09-26 09:19:56 +03:00
Udi Finkelstein 2dea42e903 Added $bits() for memories as well. 2017-09-26 09:11:25 +03:00
Udi Finkelstein 17f8b41605 $size() now works with memories as well! 2017-09-26 08:36:45 +03:00
Udi Finkelstein 64eb8f29ad Add $size() function. At the moment it works only on expressions, not on memories. 2017-09-26 06:25:42 +03:00
Clifford Wolf 30396270a2 Increase maximum LUT size in blifparse to 12 bits 2017-09-27 15:27:42 +02:00
Clifford Wolf 91d9c50bb3 Parse reals as string in JSON front-end 2017-09-26 14:37:03 +02:00
Clifford Wolf 2c04d883b1 Minor coding style fix 2017-09-26 13:50:14 +02:00
Clifford Wolf cb1d439d10 Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master 2017-09-26 13:48:13 +02:00
Clifford Wolf 2cc09161ff Fix ignoring of simulation timings so that invalid module parameters cause syntax errors 2017-09-26 01:52:59 +02:00
combinatorylogic 64ca0be971 Adding support for string macros and macros with arguments after include 2017-09-21 18:25:02 +01:00
Robert Ou 366ce87cff json: Parse inout correctly rather than as an output 2017-08-14 12:09:03 -07:00
Clifford Wolf 15073790bf Add merging of "past FFs" to verific importer 2017-07-29 00:10:38 +02:00
Clifford Wolf d4b9602cbd Add minimal support for PSL in VHDL via Verific 2017-07-28 17:39:49 +02:00
Clifford Wolf 5a828fff34 Improve Verific HDL language options 2017-07-28 15:32:54 +02:00
Clifford Wolf acd6cfaf67 Fix handling of non-user-declared Verific netbus 2017-07-28 11:31:27 +02:00
Clifford Wolf c1cfca8f54 Improve Verific SVA importer 2017-07-27 14:05:09 +02:00
Clifford Wolf 2336d5508b Add log_warning_noprefix() API, Use for Verific warnings and errors 2017-07-27 12:17:04 +02:00
Clifford Wolf d9641621d9 Add "verific -import -n" and "verific -import -nosva" 2017-07-27 11:54:45 +02:00
Clifford Wolf 90d8329f64 Improve Verific SVA import: negedge and $past 2017-07-27 11:40:07 +02:00
Clifford Wolf 147ff96ba3 Improve Verific SVA importer 2017-07-27 10:39:39 +02:00
Clifford Wolf 530040ba6f Improve Verific bindings (mostly related to SVA) 2017-07-26 18:00:01 +02:00
Clifford Wolf abd3b4e8e7 Improve "help verific" message 2017-07-25 15:13:22 +02:00
Clifford Wolf 6dbe1d4c92 Add "verific -extnets" 2017-07-25 14:53:11 +02:00