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1171 Commits

Author SHA1 Message Date
Claire Wolf 2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand 
Add Verific support for OPER_REDUCE_NAND
 2020-01-30 19:55:53 +01:00
Claire Wolf 60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help 
`verific` pass to print help message when command syntax error
 2020-01-30 18:05:16 +01:00
Claire Wolf ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69 
verific: unflatten struct ports
 2020-01-30 18:03:35 +01:00
Claire Wolf 23c44afaed Add Verific support for OPER_REDUCE_NAND 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-30 18:01:13 +01:00
Eddie Hung 6d27d43727 Add and use SigSpec::reverse() 2020-01-28 10:37:16 -08:00
Eddie Hung ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung f443695a38 Merge remote-tracking branch 'origin/master' into eddie/verific_help 2020-01-27 10:34:10 -08:00
Eddie Hung d730bba6d2 verific: no help() when no YOSYS_ENABLE_VERIFIC 2020-01-27 10:32:18 -08:00
Eddie Hung 7b445121cc verific: also unflatten for 'hierarchy' flow as per @cliffordwolf 2020-01-27 10:15:22 -08:00
Eddie Hung c7fbe13db5 read_aiger: set abc9_box_seq attr 2020-01-24 13:11:43 -08:00
Eddie Hung cccc0ae112 verific: unflatten struct ports 2020-01-24 10:12:52 -08:00
Eddie Hung 73526a6f10 read_aiger: also parse abc9_mergeability 2020-01-22 14:21:25 -08:00
Eddie Hung cd093c00f8 read_aiger: discard LUT inputs with nodeID == 0; not < 2 2020-01-21 11:56:30 -08:00
Eddie Hung 7f728bc116 read_aiger: ignore constant inputs on LUTs 2020-01-21 11:16:50 -08:00
Eddie Hung 03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung 05c8858a90 read_aiger: $lut prefix in front 2020-01-15 14:31:32 -08:00
Eddie Hung 53a99ade9c Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 11:46:56 -08:00
Eddie Hung f63f76c372 read_aiger: also rename "$0" 2020-01-14 09:01:53 -08:00
Eddie Hung 2c65e1abac abc9: break SCC by setting (* keep *) on output wires 2020-01-13 21:45:27 -08:00
Eddie Hung ee95fa959a read_aiger: uniquify wires with $aiger<autoidx> prefix 2020-01-13 21:28:27 -08:00
Eddie Hung 766e16b525 read_aiger: make $and/$not/$lut the prefix not suffix 2020-01-13 17:34:37 -08:00
Eddie Hung d979648b7a read_aiger: more accurate debug message 2020-01-09 10:02:19 -08:00
Eddie Hung 943ea4bf9e read_aiger: do not double-count outputs for flops 2020-01-09 08:55:36 -08:00
Eddie Hung 2ca8c10e7a Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-07 15:43:22 -08:00
Eddie Hung 2ac36031d4 read_aiger: consistency between ascii and binary; also name latches 2020-01-07 13:30:31 -08:00
Eddie Hung 8f5388ea5b read_aiger fixes 2020-01-07 11:59:57 -08:00
Eddie Hung b94cf0c126 read_aiger: connect identical signals together 2020-01-07 11:43:28 -08:00
Eddie Hung baba33fbd3 read_aiger: cope with latches and POs with same name 2020-01-07 11:22:48 -08:00
Eddie Hung 738af17a26 read_aiger: default -clk_name to be empty 2020-01-07 11:21:45 -08:00
Eddie Hung 61a2a60595 read_aiger: do not process box connections, work standalone 2020-01-07 09:48:11 -08:00
Eddie Hung b57f692a9e read_aiger: consistency between ascii and binary 2020-01-07 09:32:34 -08:00
Eddie Hung 83616e7866 read_aiger: add -xaiger option 2020-01-06 12:43:29 -08:00
Eddie Hung 96db05aaef parse_xaiger to not take box_lookup 2019-12-31 17:06:03 -08:00
Eddie Hung e5ed8e8e21 parse_xaiger to reorder ports too 2019-12-31 16:50:22 -08:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531 
verilog: preserve size of $genval$-s in for loops
 2019-12-19 12:21:33 -05:00
Clifford Wolf 22dd9f107c Send people to symbioticeda.com instead of verific.com 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-12-18 13:06:34 +01:00
Eddie Hung a6fdb9f5c1 aiger frontend to user shorter, $-prefixed, names 2019-12-17 15:50:01 -08:00
Eddie Hung 5f50e4f112 Cleanup xaiger, remove unnecessary complexity with inout 2019-12-17 15:45:26 -08:00
Eddie Hung 0875a07871 read_xaiger to cope with optional '\n' after 'c' 2019-12-17 15:45:26 -08:00
Eddie Hung c0339bbbf1 Name inputs/outputs of aiger 'i%d' and 'o%d' 2019-12-13 16:21:09 -08:00
Rodrigo Alejandro Melo e9dc2759c4 Fixed some missing "verilog_" in documentation 2019-12-13 10:17:05 -03:00
Eddie Hung 1ac1697e15 Stray log_dump 2019-12-11 16:59:00 -08:00
Eddie Hung af36943cb9 Preserve size of $genval$-s in for loops 2019-12-11 16:52:37 -08:00
Eddie Hung a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung ab667d3d47 Call abc9 with "&write -n", and parse_xaiger() to cope 2019-12-06 16:35:57 -08:00
Eddie Hung 69d8c1386a Do not connect undriven POs to 1'bx 2019-12-06 16:21:06 -08:00
Clifford Wolf 7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands 
Clarify semantics of comb cells, in particular shifts
 2019-12-05 08:24:24 -08:00
whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
 2019-12-04 11:59:36 +00:00