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6108 Commits

Author SHA1 Message Date
Eddie Hung 3dd0682f29 Update doc 2019-06-06 12:11:59 -07:00
Eddie Hung 030f1d30e9 Add to CHANGELOG 2019-06-06 12:04:42 -07:00
Eddie Hung b8620f7b3d One more and tidy up 2019-06-06 12:03:44 -07:00
Eddie Hung 5d4eca5a29 Add a few more special case tests 2019-06-06 11:59:41 -07:00
Eddie Hung 3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
Eddie Hung 543dd11c7e Missing file 2019-06-06 11:03:45 -07:00
Eddie Hung 7bd1c664a6 Initial adaptation of muxpack from shregmap 2019-06-06 10:51:02 -07:00
tux3 88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Clifford Wolf b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn 
Added support for parsing attributes on port connections.
 2019-06-06 12:34:05 +02:00
David Shah 30cedaca10
Merge pull request #1073 from whitequark/ecp5-diamond-iob 
ECP5: implement most Diamond I/O buffer primitives
 2019-06-06 11:22:49 +01:00
whitequark f3a26730b6 ECP5: implement all Diamond I/O buffer primitives. 2019-06-06 10:18:33 +00:00
Clifford Wolf e4e1cd6930
Merge pull request #1071 from YosysHQ/eddie/fix_1070 
Fix typo in opt_rmdff causing register to be incorrectly removed
 2019-06-06 06:50:12 +02:00
Clifford Wolf 50e2dce5e7
Merge pull request #1072 from YosysHQ/eddie/fix_1069 
Error out if no top module given before 'sim'
 2019-06-06 06:49:07 +02:00
Eddie Hung fd8ef128bf Missing doc for -tech xilinx in shregmap 2019-06-05 14:21:44 -07:00
Eddie Hung dd134914cc Error out if no top module given before 'sim' 2019-06-05 14:16:24 -07:00
Eddie Hung feb2ddb52b Fix typo in opt_rmdff 2019-06-05 14:08:14 -07:00
Eddie Hung 935df3569b shregmap -tech xilinx_static to handle INIT 2019-06-05 12:55:59 -07:00
Eddie Hung 72eda94a66 Continue support for ShregmapTechXilinx7Static 2019-06-05 12:33:55 -07:00
Eddie Hung 6ed15b7890 Update abc attributes on FD*E_1 2019-06-05 12:33:40 -07:00
Eddie Hung 67f744d428 Cleanup 2019-06-05 12:28:46 -07:00
Eddie Hung 2c18d530ea Call shregmap -tech xilinx_static 2019-06-05 12:28:26 -07:00
Eddie Hung e473e74565 Revert "Move ff_map back after ABC for shregmap" 
This reverts commit 9b9bd4e19f.
 2019-06-05 11:53:06 -07:00
Eddie Hung dfe9d95579 Add -tech xilinx_static 2019-06-05 11:14:14 -07:00
Eddie Hung e1e37db860 Refactor to ShregmapTechXilinx7Static 2019-06-05 11:08:08 -07:00
Eddie Hung 45d1bdf83a shregmap -tech xilinx_dynamic to work -params and -enpol 2019-06-05 10:21:57 -07:00
Eddie Hung a3a80b755c
Merge pull request #1067 from YosysHQ/clifford/fix1065 
Suppress driver-driver conflict warning for unknown cell types
 2019-06-05 09:59:05 -07:00
Eddie Hung bcc0a5d136 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-05 09:56:57 -07:00
Eddie Hung b5aff1de04 Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux 2019-06-05 09:56:51 -07:00
Maciej Kurc 03e0d3a17c Fixed memory leak. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-05 10:42:43 +02:00
Clifford Wolf f15b5e6309
Merge pull request #1066 from YosysHQ/clifford/fix1056 
Remove yosys_banner() from python wrapper init
 2019-06-05 10:37:39 +02:00
Clifford Wolf b33176dafb Major rewrite of wire selection in setundef -init 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 10:26:48 +02:00
Clifford Wolf 6cc60ffd67 Indent fix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:53:06 +02:00
Clifford Wolf 00d32eb73d
Merge pull request #999 from jakobwenzel/setundefInitFix 
initialize more registers in setundef -init
 2019-06-05 09:50:15 +02:00
Clifford Wolf 4190d7c094 Fix typo in fmcombine log message, fixes #1063 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:26:44 +02:00
Clifford Wolf 8a6f9977f6 Suppress driver-driver conflict warning for unknown cell types, fixes #1065 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:14:12 +02:00
Clifford Wolf dd3c333c0a Remove yosys_banner() from python wrapper init, fixes #1056 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 08:57:33 +02:00
Eddie Hung 94a5f4e609 Rename shregmap -tech xilinx -> xilinx_dynamic 2019-06-04 14:34:36 -07:00
Eddie Hung 7b186740d3 Add log_assert to ensure no loops 2019-06-04 12:01:25 -07:00
Eddie Hung 1b836c93bb Only toposort builtin and abc types 2019-06-04 11:56:58 -07:00
Eddie Hung 82d41bc2f2 Add space between -D and _ABC 2019-06-04 11:54:08 -07:00
Eddie Hung f0e93f33cf Add (* abc_flop_q *) to brams_bb.v 2019-06-04 11:53:51 -07:00
Eddie Hung 6cf092641f Fix name clash 2019-06-04 09:56:36 -07:00
Eddie Hung e260150321 Add mux_map.v for wide mux 2019-06-04 09:51:47 -07:00
Clifford Wolf 1332051f33
Merge pull request #1062 from tux3/patch-1 
README.md: Missing formatting for <tag>
 2019-06-04 14:37:10 +02:00
Tux3 c66d644b66
README.md: Missing formatting for <tag> 2019-06-04 10:45:41 +02:00
Maciej Kurc b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-04 10:42:42 +02:00
Eddie Hung 9b9bd4e19f Move ff_map back after ABC for shregmap 2019-06-03 23:43:23 -07:00
Eddie Hung 09b778744d Respect -nocarry 2019-06-03 23:42:30 -07:00
Eddie Hung 5afa42432f Fix pmux2shiftx logic 2019-06-03 23:29:45 -07:00
Eddie Hung 23a73ca624 Merge mistake 2019-06-03 23:19:22 -07:00