Add to CHANGELOG

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Eddie Hung 2019-06-06 12:04:42 -07:00
parent b8620f7b3d
commit 030f1d30e9
1 changed files with 1 additions and 0 deletions

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@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
- Added "muxpack" pass
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"