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8867 Commits

Author SHA1 Message Date
Clifford Wolf 969ab9027a Update pmgen documentation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 22:48:13 +02:00
Clifford Wolf eb80d3d43f Change pmgen default rule to reject, switch peepopt behavior to accept 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 22:47:59 +02:00
Clifford Wolf 49301b733e
Merge branch 'master' into clifford/fix1255 2019-08-15 22:44:38 +02:00
Eddie Hung c320abc3f4 xilinx_dsp to be sensitive to keep attribute 2019-08-15 12:34:11 -07:00
Eddie Hung 96ee7b9cf7 Simplify 2019-08-15 12:30:46 -07:00
Eddie Hung 7f10019610 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-15 12:19:51 -07:00
Eddie Hung 261daffd9d Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-15 12:19:47 -07:00
Eddie Hung 27d5df9467 ffH -> ffFJKG 2019-08-15 12:19:34 -07:00
Eddie Hung 6cd8cace0c Fix 2019-08-15 11:25:42 -07:00
Eddie Hung 847c54088e Change signature of parse_blif to take IdString 2019-08-15 10:26:24 -07:00
Eddie Hung 02dead2e60 ID(\\.*) -> ID(.*) 2019-08-15 10:25:54 -07:00
Eddie Hung 467c34eff0 Convert a few more to ID 2019-08-15 10:24:35 -07:00
Eddie Hung 78ba8b8574 Transform all "\\*" identifiers into ID() 2019-08-15 10:19:29 -07:00
Eddie Hung 9f98241010 Transform "$.*" to ID("$.*") in passes/techmap 2019-08-15 10:05:08 -07:00
Clifford Wolf 03f98d9176 Add demo_reduce pass to demonstrace recursive pattern matching 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 18:36:39 +02:00
Clifford Wolf 73bf453929 Improvements in pmgen for recursive patterns 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 18:35:56 +02:00
Eddie Hung 4cfefae21e More use of IdString::in() 2019-08-15 09:23:57 -07:00
Eddie Hung d8a2aaa463
Merge pull request #1297 from YosysHQ/eddie/fix_1284_again 
extract_fa: Un-inverting AND with an inverted input also inverts input to X{,N}OR
 2019-08-15 07:49:02 -07:00
Eddie Hung 91f6cdfef6 Merge remote-tracking branch 'origin/master' into eddie/fix_1284_again 2019-08-15 06:48:40 -07:00
Clifford Wolf 704686774e
Merge pull request #1275 from YosysHQ/clifford/ids 
New ID() macro and now also use it
 2019-08-15 12:03:16 +02:00
Clifford Wolf 85b0b2c589
Merge branch 'master' into clifford/ids 2019-08-15 10:22:59 +02:00
Clifford Wolf 5422007400
Merge pull request #1295 from YosysHQ/eddie/fix_travis 
Fix Travis CI
 2019-08-15 10:20:22 +02:00
Eddie Hung 1551e14d2d AND with an inverted input, causes X{,N}OR output to be inverted too 2019-08-14 16:26:24 -07:00
Eddie Hung 1e47e81869 Revert "Only sort leaves on non-ANDNOT/ORNOT cells" 
This reverts commit 5ec5f6dec7.
 2019-08-14 15:23:25 -07:00
Eddie Hung 4c2a2e275f Revert earliest to gcc-4.8, compile iverilog with default compiler 2019-08-14 12:28:17 -07:00
Eddie Hung 182659f114 Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" 
This reverts commit c82b2fa31f.
 2019-08-14 12:26:45 -07:00
Eddie Hung e517c1c913 Remove .0 from clang-8.0 2019-08-14 12:23:15 -07:00
Eddie Hung c82b2fa31f Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! 2019-08-14 12:16:02 -07:00
Eddie Hung 2df432af03 bionic -> xenial as its on whitelist 2019-08-14 11:52:08 -07:00
Eddie Hung 0c003a3d0d Bump gcc from 4.8 to 4.9 as undefined reference 
... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
 2019-08-14 11:26:32 -07:00
Eddie Hung 5ec5f6dec7 Only sort leaves on non-ANDNOT/ORNOT cells 2019-08-14 11:25:56 -07:00
Eddie Hung e2797f1308
Merge pull request #1294 from YosysHQ/revert-1288-eddie/fix_1284 
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
 2019-08-14 10:42:18 -07:00
Eddie Hung 0e128510c0
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves" 2019-08-14 10:40:53 -07:00
Eddie Hung aad97168b0 Fixes for reverting SigSpec helper functions 2019-08-14 10:22:33 -07:00
Eddie Hung 2f04beeeb5 Perform C -> PCIN optimisation after pattern matcher 2019-08-13 17:11:35 -07:00
Eddie Hung 1b0e68db94 Revert changes to RTLIL::SigSpec methods 2019-08-13 17:09:28 -07:00
Eddie Hung e35dfc5ab5 Only swap ports if $mul and not $__mul 2019-08-13 16:52:15 -07:00
Marcin Kościelnicki 2d5d82e2b6 README updates 2019-08-13 21:47:27 +02:00
Marcin Kościelnicki 3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung ed4b2834ef Add assign PCOUT = P to DSP48E1 2019-08-13 12:19:26 -07:00
Marcin Kościelnicki 49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Eddie Hung 0597a3ea23 Rename to XilinxDspPass 2019-08-13 10:23:07 -07:00
Eddie Hung 2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
Eddie Hung 19d6b8846f
Merge pull request #1288 from YosysHQ/eddie/fix_1284 
Since $_ANDNOT_ is not symmetric, do not sort leaves
 2019-08-13 09:06:11 -07:00
Clifford Wolf 0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
David Shah edff79a25a xilinx: Rework labels for faster Verilator testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-13 10:29:42 +01:00
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung 8a2480526f Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00