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2454 Commits

Author SHA1 Message Date
Clifford Wolf acfaeb8d34 Added equiv_remove 2015-01-25 14:20:22 +01:00
Clifford Wolf 66a6b86daa Added equiv_miter 2015-01-25 14:00:49 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf 8fe9ab50e5 Added #ifdef NDEBUG for log_assert() 2015-01-24 11:49:34 +01:00
Clifford Wolf 909a95182b Fixed xilinx FDSE sim model 2015-01-24 11:03:22 +01:00
Clifford Wolf 75bbeb828a Various equiv_* improvements 2015-01-24 00:32:24 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf 1cb4c925d0 Improvements in equiv_make, equiv_induct 2015-01-22 21:23:01 +01:00
Clifford Wolf 5707ba22c1 Improved xdot calling 2015-01-22 20:45:53 +01:00
Clifford Wolf f6d94e8720 Added equiv_induct 2015-01-22 14:03:18 +01:00
Clifford Wolf a6aa32e762 Various equiv_simple improvements 2015-01-22 13:42:04 +01:00
Clifford Wolf 0a225f8b27 Moved equiv stuff to passes/equiv/ 2015-01-22 12:03:15 +01:00
Clifford Wolf abf8398216 Progress in equiv_simple 2015-01-21 23:59:58 +00:00
Clifford Wolf 74e1de1fac Fixed opt_muxtree performance bug 2015-01-21 16:44:07 +01:00
Clifford Wolf 0bfec8e24c Faster "make clean-abc" 2015-01-20 23:17:53 +00:00
Clifford Wolf 81020269b2 README stuff 2015-01-20 20:59:50 +00:00
Clifford Wolf 5febbe3620 Added equiv_simple 2015-01-19 15:08:44 +01:00
Clifford Wolf 615c2e136e Added equiv_status 2015-01-19 14:20:04 +01:00
Clifford Wolf 76c5d863c5 Added equiv_make command 2015-01-19 13:59:08 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf 3a58b8d5b5 Merge branch 'master' of github.com:cliffordwolf/yosys 2015-01-18 19:47:06 +01:00
Clifford Wolf d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Clifford Wolf 8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf f6f51cd68a Merge pull request #47 from mschmoelzer/master 
Add "echo-yosys-ver" and "echo-git-rev" Makefile targets.
 2015-01-18 16:39:55 +01:00
Martin Schmölzer 026b94a6f1 Add "echo-yosys-ver" and "echo-git-rev" Makefile targets. 
These Makefile targets simply echo the corresponding Makefile variable,
simplifying package build scripts.

Signed-off-by: Martin Schmölzer <mschmoelzer@gmail.com>
 2015-01-18 16:20:57 +01:00
Clifford Wolf 694cc01f1d improvements in muxtree/select_leaves test 2015-01-18 13:24:01 +01:00
Clifford Wolf f630868bc9 Improvements in opt_muxtree 2015-01-18 12:57:36 +01:00
Clifford Wolf d3b35017f8 More opt_muxtree cleanups 2015-01-18 12:13:18 +01:00
Clifford Wolf 0217ea0fb8 Added hashlib::idict<> 2015-01-18 12:12:33 +01:00
Clifford Wolf 61192514e3 Various cleanups and improvements in opt_muxtree 2015-01-18 11:17:56 +01:00
Clifford Wolf 279a18c9a3 Added synth_xilinx -retime -flatten 2015-01-17 20:47:18 +01:00
Clifford Wolf 8658eed52a Added support for memories to flatten (techmap) 2015-01-17 20:46:52 +01:00
Clifford Wolf 7031231145 Added MUXCY and XORCY support to synth_xilinx 2015-01-17 15:39:54 +01:00
Clifford Wolf a95c229e12 Fixed a bug in opt_muxtree for "mux forests" 2015-01-17 13:56:53 +01:00
Clifford Wolf 3628ca989c Improved opt_muxtree 2015-01-17 12:05:19 +01:00
Clifford Wolf b32ba6f568 Optimizing no-op cell->setPort() 2015-01-17 12:04:40 +01:00
Clifford Wolf 8ce8a230f4 Bugfix in dff2dffe 2015-01-16 17:51:17 +01:00
Clifford Wolf 3ed4e34380 Added cells.lib 2015-01-16 15:50:42 +01:00
Clifford Wolf dff8bd3b2a Added dff2dffe to synth_xilinx 2015-01-16 15:49:15 +01:00
Clifford Wolf 7bde74cd2a Added more FF types to xilinx/cells.v 2015-01-16 15:24:54 +01:00
Clifford Wolf 6b09153320 Fixed xilinx bram clock inverted config 2015-01-16 15:11:56 +01:00
Clifford Wolf fd8c8d4fd3 Added FF cells to xilinx/cells_sim.v 2015-01-16 14:59:40 +01:00
Clifford Wolf b197279f3c Added Xilinx MUXF7 and MUXF8 support 2015-01-15 13:50:04 +01:00
Clifford Wolf 2e36faeced Added "abc -lut w1:w2" 2015-01-15 13:37:48 +01:00
Clifford Wolf 9065fb25cc Fixed handling of foo.__TECHMAP_... 2015-01-15 13:36:57 +01:00
Clifford Wolf df9d096a7d Ignoring more system task and functions 2015-01-15 13:08:19 +01:00
Clifford Wolf a588a4a5c9 Fixed handling of "input foo; reg [0:0] foo;" 2015-01-15 12:53:12 +01:00
Clifford Wolf 8e8e791fb5 Consolidate "Blocking assignment to memory.." msgs for the same line 2015-01-15 12:41:52 +01:00
Clifford Wolf 153d3dd4e0 Various cleanups in synth_xilinx command 2015-01-13 13:20:32 +01:00
Clifford Wolf 8426884b40 Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim) 2015-01-13 13:20:09 +01:00