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180 Commits

Author SHA1 Message Date
Clifford Wolf 08a4af3cde Improvements in BLIF front-end 2015-05-24 08:03:21 +02:00
Clifford Wolf 4744bb95fb Some fixes for $mem in verilog back-end 2015-05-20 13:55:50 +02:00
Clifford Wolf 42348cddd9 Merge pull request #63 from wluker/verilog-backend-mem 
Fixed bug in $mem cell verilog code generation.
 2015-05-11 21:38:06 +02:00
luke whittlesey 3bb5f064b8 Fixed bug in $mem cell verilog code generation. 2015-05-11 14:05:18 -04:00
Clifford Wolf 9e56739634 Disabled broken $mem support in verilog backend 2015-05-10 21:38:41 +02:00
luke whittlesey 6de8fea2c7 Made changes recommended by Clifford Wolf ... 
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
 2015-05-10 11:33:24 -04:00
luke whittlesey 2c1e150297 Verilog backend for $mem cells should now be able to handle different 
write-enable bits and RD_TRANSPARENT parameter settings.
 2015-05-08 15:29:51 -04:00
luke whittlesey c0b68f4848 Added support for $mem cells in the verilog backend. 2015-05-07 13:03:09 -04:00
Clifford Wolf d176e613c2 Minor fixes in handling of "init" attribute 2015-04-09 15:12:26 +02:00
Clifford Wolf aa0ab975b9 Removed "techmap -share_map" (use "-map +/filename" instead) 2015-04-08 12:13:53 +02:00
Clifford Wolf c0e2b3eb11 Added "port_directions" to write_json output 2015-04-06 01:49:58 +02:00
Clifford Wolf b0c0ede879 Added "init" attribute support to verilog backend 2015-04-04 18:06:52 +02:00
Ahmed Irfan 13e2e71ebe Update README 
corrected url
 2015-04-03 17:11:45 +02:00
Ahmed Irfan ed750f0a55 Delete btor.ys 
.ys script not needed
 2015-04-03 16:45:54 +02:00
Ahmed Irfan e82e4f7df4 Update README 
pmux cell is implemented
 2015-04-03 16:45:14 +02:00
Ahmed Irfan ea2e0297d5 separated memory next from write cell 2015-04-03 16:41:50 +02:00
Clifford Wolf 67e6dcd34a Added Verilog backend $dffsr support 2015-03-18 08:01:37 +01:00
Clifford Wolf 6c8fdb1829 Documentation for JSON format, added attributes 2015-03-06 10:21:21 +01:00
Clifford Wolf adc12ce46e Json bugfix 2015-03-03 09:41:41 +01:00
Clifford Wolf 4fc63f27a1 Json backend improvements 2015-03-03 09:28:44 +01:00
Clifford Wolf 795a6e1d04 Added write_blif -attr 2015-03-02 23:47:45 +01:00
Clifford Wolf 8b488983d0 Added JSON backend 2015-03-02 23:30:58 +01:00
Clifford Wolf 5d4f513c3b Added $assume support to write_smt2 2015-02-26 19:02:55 +01:00
Clifford Wolf ff3f2448b1 Minor "write_smt2" help msg change 2015-02-22 16:30:02 +01:00
Clifford Wolf 4b89dd983c Added "<mod>_a" and "<mod>_i" to write_smt2 output 2015-02-22 16:19:10 +01:00
Clifford Wolf 756b4064b2 Fixed "write_verilog -attr2comment" handling of "*/" in strings 2015-02-13 22:48:10 +01:00
Clifford Wolf 6978f3a77b Added EDIF backend support for multi-bit cell ports 2015-02-01 15:43:35 +01:00
Clifford Wolf fb8c755726 Shorter "dump" options 2015-01-31 23:52:36 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf 146f769bee Cosmetic changes in verilog output format 2015-01-02 22:57:08 +01:00
Clifford Wolf eefe78be09 Fixed memory->start_offset handling 2015-01-01 12:56:01 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf e8c12e5f0c Various fixes and improvements in "write_smt2 -bv" 2014-12-25 20:28:34 +01:00
Clifford Wolf 68233baa1f Various fixes and improvements in write_smt2 2014-12-25 17:52:31 +01:00
Clifford Wolf 95f17dbab0 Added support for most BV cell types to write_smt2 2014-12-25 15:37:02 +01:00
Clifford Wolf 1c3d51375f Added "write_smt2 -bv" and other write_smt2 improvements 2014-12-25 13:30:20 +01:00
Clifford Wolf e548483c91 Added write_smt2 (only gate level logic supported so far) 2014-12-24 16:17:57 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 5df192e71c Added $dffe support to write_verilog 2014-12-20 00:03:20 +01:00
Clifford Wolf 30de490d86 Fixed another bug in write_blif handling of $lut cells 2014-12-19 17:54:44 +01:00
Clifford Wolf b95051fb70 Fixed writing of $lut cells in BLIF backend 2014-12-17 11:13:57 +01:00
Clifford Wolf e01254d824 Added "write_blif -undef" and support for special "-" true/false/undef type 2014-12-14 18:00:38 +01:00
Clifford Wolf 59d11978fc Added "write_blif -blackbox" 
based on code by Eddie Hung from
https://github.com/eddiehung/yosys/commit/1e481661cb4a4
 2014-12-14 17:45:03 +01:00
Clifford Wolf 32dce4a870 Added "blif -unbuf" feature 2014-12-14 17:37:46 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf 461594bb83 Fixed generation of temp names in verilog backend 2014-11-07 14:40:06 +01:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00