Eddie Hung
06f8f2654a
Working
2019-03-15 19:13:40 -07:00
Eddie Hung
8af9979aab
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
...
This reverts commit 26ecbc1aee
.
2019-03-14 09:01:48 -07:00
Eddie Hung
f1a8e8a480
Merge remote-tracking branch 'origin/master' into xc7srl
2019-03-14 08:59:19 -07:00
Eddie Hung
26ecbc1aee
Add shregmap -init_msb_first and use in synth_xilinx
2019-03-14 08:10:02 -07:00
Larry Doolittle
61fc411c5d
Clean up some whitepsace outliers
2019-02-26 09:39:46 -08:00
David Shah
58c22dae31
abc: Improved recovered netnames, also preserve src on nets with dress
...
Signed-off-by: David Shah <davey1576@gmail.com>
2019-02-06 22:23:13 +01:00
David Shah
8524a479b1
abc: Preserve naming through ABC using 'dress' command
...
Signed-off-by: David Shah <dave@ds0.me>
2019-02-06 22:23:13 +01:00
whitequark
e792bd56b7
flowmap: clean up terminology.
...
* "map": group gates into LUTs;
* "pack": replace gates with LUTs.
This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.
Also clean up some other log messages while we're at it.
2019-01-08 02:05:06 +00:00
whitequark
211c26a4c9
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00
whitequark
8b44198e23
flowmap: construct a max-volume max-flow min-cut, not just any one.
2019-01-06 19:51:37 +00:00
whitequark
2fcc1ee72e
flowmap: add -minlut option, to allow postprocessing with opt_lut.
2019-01-04 21:18:03 +00:00
whitequark
9bc5cf0844
flowmap: cleanup for clarity. NFCI.
2019-01-04 13:04:20 +00:00
whitequark
fd21564deb
flowmap: improve debug graph output. NFC.
2019-01-04 03:30:04 +00:00
whitequark
7850a0c28a
flowmap: add link to longer version of paper. NFC.
2019-01-04 02:33:10 +00:00
whitequark
07af772a72
flowmap: new techmap pass.
2019-01-03 14:28:19 +00:00
Icenowy Zheng
256fb8c95c
Add "dffinit -noreinit" parameter
...
Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.
Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 23:10:40 +08:00
Icenowy Zheng
fec8b3c81f
Add "dffinit -strinit high low"
...
On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".
Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 15:37:43 +08:00
Clifford Wolf
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:31 +01:00
Clifford Wolf
0d9c850a07
Merge pull request #735 from daveshah1/trifixes
...
deminout fixes
2018-12-16 16:02:21 +01:00
Clifford Wolf
a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
...
Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
David Shah
4c59447168
deminout: Consider $tribuf cells
...
Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
David Shah
d3fe9465f3
deminout: Don't demote constant-driven inouts to inputs
...
Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
David Shah
1dfb2fecab
abc: Preserve naming through ABC using 'dress' command
...
Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 15:05:07 +00:00
whitequark
d1f2cb01dc
lut2mux: handle 1-bit INIT constant in $lut cells.
...
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
2018-12-05 19:27:48 +00:00
Clifford Wolf
c800e3bb16
Fix typo
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-04 23:30:23 +01:00
Sylvain Munaut
8d3ab626ea
dff2dffe: Add option for unmap to only remove DFFE with low CE signal use
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Niels Moseley
cfc9b9147c
DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info.
2018-11-06 12:11:52 +01:00
Clifford Wolf
719e29404a
Allow square brackets in liberty identifiers
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-05 12:33:33 +01:00
Niels Moseley
04cd179696
Liberty file newline handling is more relaxed. More descriptive error message
2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a
Report an error when a liberty file contains pin references that reference non-existing pins
2018-11-03 18:07:51 +01:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
...
Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
0eaab6cd1d
Add missing <deque> include (MSVC build fix)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 15:21:59 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
459d367913
ecp5: Adding synchronous set/reset support
...
Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-14 16:18:01 +02:00
Clifford Wolf
675a44b41a
Be slightly less aggressive in "deminout" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-19 14:29:38 +02:00
Robert Ou
9763e4d830
Fix infinite loop in abc command under emscripten
2018-05-18 22:42:39 -07:00
Robert Ou
bfce3a7479
Add an option to statically link abc into yosys
...
This is currently incomplete because the output filter no longer works.
2018-05-18 22:35:28 -07:00
Clifford Wolf
fe80b39f56
Fix iopadmap for loops between tristate IO buffers
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 14:02:27 +02:00
Clifford Wolf
edd297fb1c
Fix iopadmap for cases where IO pins already have buffers on them
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 13:13:43 +02:00
Clifford Wolf
145c685de0
Add ABC FAQ to "help abc"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-04 21:59:31 +02:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Clifford Wolf
705c366a91
Added missing dont_use handling for SR FFs to dfflibmap
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-05 11:01:45 +02:00
Clifford Wolf
a74f805ba0
Fix handling of src attributes in flatten
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 13:55:30 +01:00
Clifford Wolf
9ac560f5d3
Add "dffinit -highlow" and fix synth_intel
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-09 18:42:19 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Staf Verhaegen
92eb841f0a
Value of properties can be expression.
...
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:
input_voltage(CMOS) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
Current implementation just parses the expression but no interpretation is done.
2018-01-03 21:37:17 +00:00
Clifford Wolf
7c57d8fbb4
Rewrite ABC output to include proper net names in timing report
2017-10-10 13:32:58 +02:00
Andrew Zonenberg
2b65b65d70
Added missing "break"
2017-09-15 17:54:52 -07:00
Andrew Zonenberg
7b3966714c
Implemented off-chain support for extract_reduce
2017-09-15 13:59:18 -07:00
Andrew Zonenberg
3404934c9c
extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored.
2017-09-15 13:59:05 -07:00