Eddie Hung
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037d1a03df
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Add #1460 testcase
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2019-12-12 17:49:55 -08:00 |
Eddie Hung
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7a9d1be97d
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Add memory rules for RAM16X1D, RAM32M, RAM64M
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2019-12-12 17:44:59 -08:00 |
Eddie Hung
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caab66111e
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Rename memory tests to lutram, add more xilinx tests
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2019-12-12 17:44:37 -08:00 |
Diego H
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751a18d7e9
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Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
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2019-12-12 17:32:58 -06:00 |
Eddie Hung
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fce6bad6ae
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Remove 'clkpart' entry in CHANGELOG
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2019-12-12 15:02:46 -08:00 |
Eddie Hung
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bea15b537b
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-12 14:57:17 -08:00 |
Eddie Hung
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9ab1feeaf1
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abc9_map.v: fix Xilinx LUTRAM
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2019-12-12 14:56:52 -08:00 |
Eddie Hung
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3eed8835b5
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abc9_map.v: fix Xilinx LUTRAM
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2019-12-12 14:56:15 -08:00 |
Diego H
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e33f407655
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Adding a note (TODO) in the memory_params.ys check file
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2019-12-12 16:06:46 -06:00 |
N. Engelhardt
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1187e91c2f
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add test and make help message more verbose
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2019-12-12 20:51:59 +01:00 |
Diego H
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937ec1ee78
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Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
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2019-12-12 13:50:36 -06:00 |
Diego H
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ab6ac8327f
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Merge https://github.com/YosysHQ/yosys into bram_xilinx
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2019-12-12 13:40:05 -06:00 |
Eddie Hung
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23fcfd0adb
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Make SV2017 compliant courtesy of @wsnyder
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2019-12-12 07:34:07 -08:00 |
N. Engelhardt
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4c7cda1c8b
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add a command to read/modify scratchpad contents
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2019-12-12 16:25:03 +01:00 |
Eddie Hung
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1ac1697e15
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Stray log_dump
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2019-12-11 16:59:00 -08:00 |
Eddie Hung
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af36943cb9
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Preserve size of $genval$-s in for loops
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2019-12-11 16:52:37 -08:00 |
Eddie Hung
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151f7533e8
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Add testcase
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2019-12-11 16:52:37 -08:00 |
Eddie Hung
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2666482282
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Update README.md :: abc_ -> abc9_
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2019-12-11 16:38:43 -08:00 |
Eddie Hung
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f022645cd2
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Fix bitwidth mismatch; suppresses iverilog warning
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2019-12-11 13:02:07 -08:00 |
Gustavo Romero
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993a77d19b
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manual: Fix text in Abstract section
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2019-12-11 08:22:08 -03:00 |
David Shah
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613334d9dc
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Merge pull request #1564 from ZirconiumX/intel_housekeeping
Intel housekeeping
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2019-12-11 08:46:10 +00:00 |
Dan Ravensloft
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85a14895ca
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synth_intel: a10gx -> arria10gx
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2019-12-10 13:48:10 +00:00 |
Dan Ravensloft
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eab3272cde
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synth_intel: cyclone10 -> cyclone10lp
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2019-12-10 13:47:58 +00:00 |
Eddie Hung
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7e5602ad17
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Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
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2019-12-09 17:38:48 -08:00 |
Eddie Hung
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49c2e59b2a
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Fix comment
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2019-12-09 15:44:19 -08:00 |
Eddie Hung
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fb203d2a2c
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ice40_opt to restore attributes/name when unwrapping
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2019-12-09 14:29:29 -08:00 |
Eddie Hung
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36a88be609
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ice40_wrapcarry -unwrap to preserve 'src' attribute
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2019-12-09 14:28:54 -08:00 |
Eddie Hung
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eff858cd33
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unmap $__ICE40_CARRY_WRAPPER in test
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2019-12-09 14:20:35 -08:00 |
Eddie Hung
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bbdf2452b3
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-unwrap to create $lut not SB_LUT4 for opt_lut
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2019-12-09 13:27:09 -08:00 |
Eddie Hung
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500ed9b501
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Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
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2019-12-09 12:45:22 -08:00 |
Eddie Hung
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e05372778a
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ice40_wrapcarry to really preserve attributes via -unwrap option
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2019-12-09 11:48:28 -08:00 |
David Shah
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184c0e796a
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ecp5: Add support for mapping PRLD FFs
Signed-off-by: David Shah <dave@ds0.me>
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2019-12-07 13:04:36 +00:00 |
Eddie Hung
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a46a7e8a67
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-06 23:22:52 -08:00 |
Eddie Hung
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ecb0c68f07
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Merge pull request #1555 from antmicro/fix-macc-xilinx-test
tests: arch: xilinx: Change order of arguments in macc.sh
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2019-12-06 23:04:04 -08:00 |
Eddie Hung
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946d5854c0
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Drop keep=0 attributes on SB_CARRY
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2019-12-06 17:27:47 -08:00 |
Eddie Hung
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91467938c4
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Stray newline
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2019-12-06 17:08:19 -08:00 |
Eddie Hung
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f2ac36de4a
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write_xaiger to inst each cell type once, do not call techmap/aigmap
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2019-12-06 17:06:10 -08:00 |
Eddie Hung
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98c9ea605b
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techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
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2019-12-06 17:05:02 -08:00 |
Eddie Hung
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ab667d3d47
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Call abc9 with "&write -n", and parse_xaiger() to cope
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2019-12-06 16:35:57 -08:00 |
Eddie Hung
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c767525441
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Remove creation of $abc9_control_wire
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2019-12-06 16:23:09 -08:00 |
Eddie Hung
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69d8c1386a
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Do not connect undriven POs to 1'bx
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2019-12-06 16:21:06 -08:00 |
Eddie Hung
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fce527f4f7
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Fix abc9 re-integration, remove abc9_control_wire, use cell->type as
as part of clock domain for mergeability class
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2019-12-06 16:20:18 -08:00 |
Eddie Hung
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1f96de04c9
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Fix writing non-whole modules, including inouts and keeps
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2019-12-06 16:19:10 -08:00 |
Jan Kowalewski
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dcb30b5f4a
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tests: arch: xilinx: Change order of arguments in macc.sh
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2019-12-06 09:15:49 +01:00 |
Eddie Hung
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ec0acc9f85
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abc9 to use mergeability class to differentiate sync/async
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2019-12-06 00:12:37 -08:00 |
Eddie Hung
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a682a3cf93
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write_xaiger to support part-selected modules again
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2019-12-05 17:54:43 -08:00 |
Eddie Hung
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01a3cc29ba
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abc9 to do clock partitioning again
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2019-12-05 17:26:22 -08:00 |
Eddie Hung
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02786b0aa0
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Remove clkpart
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2019-12-05 17:25:26 -08:00 |
Eddie Hung
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864bff14f1
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Revert "Special abc9_clock wire to contain only clock signal"
This reverts commit 6a2eb5d8f9 .
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2019-12-05 11:11:53 -08:00 |
Clifford Wolf
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7dece7955e
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Merge pull request #1551 from whitequark/manual-cell-operands
Clarify semantics of comb cells, in particular shifts
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2019-12-05 08:24:24 -08:00 |