* New: In NetBuilderHybridVH::_do_1G_xM1_1PinM1(), added configuration
to manage pins on the north/south sides for VH,2RL.
* Bug: In NetBuilderHybridVH::doRp_xG_xM1_xM3(), correct misplaced
vertical creation (buildind invalid topologies).
* New: EtesianEngine::toColoquinte(), display histograms of the cells
widths (in pitch) before and after bloating to get a better feeling
of the behavior.
* New: In EtesianEngine, add support for track avoidance. Portions of
tracks to avoid are specified by a Box, which should flat and on
the axis of the request track. This feature is used by the H-Tree
to clear the vertical tracks under the tree from any terminal.
* New: In Etesian::Area, Slice and SubSlice, add support for track
avoidance. Exported to the Python wrapper.
* New: SubSlice::getUsedVTracks() to get a set of tracks blocked by
the cell.
* New: SubSlice::trackAvoid(), shift left/rigth the cell under the
requested vertical track. Try only to move the cell under the
track and not it's neighbor, so it assume that there is sufficient
space left or right of the cell.
* Bug: In cumulus/plugins.block.configuration.BlockConf, the Cfg
parameters may be read too early from the Cfg space into the
various sub-conf objects (like FeedsConf). Delay the reading
of the parameters in a _postInit() functions.
Modify Block and CoreToChip to call _postInit().
* New: In cumulus/plugins.block.configuration.BlockConf._loadRoutingGauge,
allow the cell gauge name to differ from the routing gauge name.
* New: In cumulus/plugins.block.configuration.FeedsConf, allow to
select the default feed to be used with 'etesian.defaultFeed'
parameter.
* New: In cumulus/plugins.block.spares.BufferPool, allow to control
whether or not we want tie to either side of the pool.
(for latch up).
* New: In cumulus/plugins.block.HTree._connectLeaf(), add support
for track avoidance.
* Bug: In cumulus/plugins.block.HTree._connectLeaf(), the TL2 contact,
the one on the *top* auxiliary buffer seemed to have been badly
positioned until now (too low, not using tl2Y).
This is strange because it should have caused disconnections,
but I didn't see it in the wiring and the regressions tests didn't
flag anything wrong. Still a bit weird and worrying.
Previously, the relevant NetBuilder and routing strategies where
directly guessed from the RoutingGauge traits. This is no longer
doable as the combinations increases. Now to configure both the
global and detailed router we need three "parameters" :
1. The routing gauge itself (tells which layers are in which
directions) and how to make the VIAs.
2. The NetBuilder to use, they are identified by strings.
Currently we support:
* "HV,3RL+", for all SxLib derived standard cells.
* "VH,2RL", for hybrid routing (over the cell, but terminals
are also in the first RL).
* "2RL-", for strict channel routing.
* "VH,3RL+", an attempt for FreePDK 45, not optimized enough
to be considered as usable.
3. The routing style, mostly affect the way the GCell grid will be
built.
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
Thoses three parameters are partly overlapping and must be sets in
a consistent manner, otherwise strange results may occurs.
* New: CRL::RoutingGauge::getFirstRoutingGauge(), to get the lowest
layer available for routing (not a PinOnly, not a PowerSupply).
* Change: In CRL::RoutingGauge::isHV() and isVH(), were previously
always returning false when the gauge was 2RL only. Now, check
on the first usable RL.
* Bug: In cumulus/plugins.block.configuration._loadRoutingGauge(),
there was a bad computation of the deep RLs when the top layer
was not defined. Occured for 2RL gauges only.
* Bug: In Anabatic::RpsInRow::slacken() (LayerAssign), forgotten curly braces
in the test to skip METAL2 terminals.
* Change: In Etestian::BloatChannel::getDx(), adjust the bloating
policy to converge on Arlet6502. Always ensure that there is
a 50% ratio between terminal used V-tracks and free ones.
If there is more than 80% of terminals, add one more track.
* Bug: In AnabaticEngine & KatanaEngine, KatanaEngine is a derived
class of AnabaticEngine. They uses Anabatic::Configuration
and Katana::Configuration that also derives from each other.
I though I had made one configuration attribute in the base
class that was using the right Configuration. But no. I did
have two configurations attributes, one in AnabaticEngine and
one in KatanaEngine, the later "shadowing" the former. As a
results, parameters modified in AnabaticEngine, *after* the
initial creation of the tool *where never seen* at Katana
level (due to it's own duplicate). What a mess.
Now there is only one attribute in the *base* class Anabatic,
which is created through a new virtual function _createConfiguration()
called in _postCreate() which allocate the right Configuration
according to the dynamic type of the tool (KatanaEngine).
In KatanaEngine, access the configuration through the
attribute (_configuration) and not the accessor (getConfiguration()).
* Bug: In KatanaEngine, no longer directly use the _configuration attribute
(which is not accessible anyway) but the getConfiguration() accessor.
The accessor perform a static_cast from the Super::getConfiguration()
into Katana::Configuration.
Complete cleanup of the various configuration accessors.
* New: AnabaticEngine::setupNetBuilder(), perform an early check
of the requested NetBuilderStyle. The NetBuilderStyle is just a
string that will be matched against the (hard-coded) supported
NetBuilders. Then check the topological characteristics against
the capabilities of the gauge (HV, VH and so on).
Still a bit too hard-coded for now.
This function has been split from AnabaticEngine::_loadGrByNet().
* Change: AnabaticEngine::isChannelStyle() renamed from isChannelMode().
* New: In Anabatic::Configuration, two new attributes to select the
topology and routing style:
- _netBuilderStyle to explicitely select the NetBuilder to use.
It's a string, which is provided by each NetBuilder.
- _routingStyle to define how the overall routing will work.
It's a set of flags (StyleFlags):
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
* New: In anabatic/Constants, add StyleFlags to define how the router
should operate (see above).
* Bug: In Anabatic::GCell, in CTOR, no reason to set up the HChannelGCell flag.
* Bug: In Anabatic::GCell::updateDensity(), when computing layers non contiguous
saturation, do not systematically skip RL 0, but only if it's PinOnly.
* Change: In Anabatic::NetBuilder, rename isTwoMetal by isStrictChannel.
* Change: In Anabatic::NetBuilderHV, rename doRp_AccessNorthPin() in
doRp_AccessNorthSouthPin(). More accurate.
* Bug: In NetBuilderHV::_do_1G_xM1_1PinM2(), the wires to connect the M1
terminals where created *twice*. Uterly stupid, there where placed in
overlap by the router!
* New: In AnabaticEngine, new accessors to the NetBuilderStyle and
RoutingStyle, proxies towards Configuration.
* Bug: In Manipulator::relax(), if there are two doglegs to be done, but
they are in the same GCell, only do one (the conflicting interval)
is short.
* Change: In Katana::Session, rename isChannelMode() into isChannelStyle().
* Change: In TrackSegment::isUnbreakable() and isStrap(), return false
when the base segment is a *weak global* (aligned with a global one).
* Change: In Katana::Row::createChannel(), correctly distinguish between
*strict channel* style and *hybrid* style. Tag the GCells as std cells
row or channels only in the former case.
* New: Hurricane::ErrorWidget, new widget exported to Python to replace
helpers.io.ErrorWidget.
* New: Hurricane::AboutWindow, new window exported to Python to replace
cumulus/plugins.aboutwindow.AboutWidget.
* Change: In cumulus/plugins.sram.sram_256x32, add a new parameter to
__init__() so the user can choose the model name of the generated
SRAM.
* Change: In cumulus/plugins.sram.sram.BaseSRAM.placeInstance(),
placement status must be FIXED instead of PLACED so the placer do
not "unplace" them.
The Cell.updatePlacedFlag() method must also be called once
the model if fully built.
* Change: In CRL/helpers.io, the ErrorWidget requires PyQt5 to execute but
is not mandatory to run Coriolis/cgt. In order to be more portable,
if it is not availble just evert to text display on the console.
This widget will be directly supplied by Coriolis in the future
completely removing the need for PyQt.
*Change: In cumulus/plugins/aboutwindow, same as above.
* New: In cumulus/plugins/sram_256x32.py, build the output mux using a
NAND2/NOR2 binary tree instead of mux2/mux3. Use more, but much
smaller cells. The reduction of wirelength (from Yosys) goes
from 4% to 15% for the non-folded variant.
Uses a specially placed tree to minimize wire length.
* New: In cumulus/plugins/sram.py, extend StdCellConf to convert names
accross library flavors (FlexLib_TSMC_C180, FlexLib_Sky130 and
generic SxLib).
The generator as been build in two parts:
1. A genereric sram.BaseSRAM class to provides support for all kind of
SRAM (grouping column tree, headers, folding).
2. The specific SRAM_256x32 (256 words of 32 bits) suited for the
ethmac.
The sram has been simulated with genpat+asimut and gives identical
results to the Yosys one (at gate level). No timing though.
* Bug: In cumulus/plugins.block.htree.HTree._connectLeaf(), the stacked
contact to connect the top left buffer amplifier was not forcibly
aligned on the vertical METAL5. In some configuaration it was
leading to gaps at METAL5 level.
* Bug: In cumulus/plugins/rsave.py, the Cells where saveds each time
one instance of was encountered. Resulting in multiple saves.
It was, of course, ineficient, but it also triggers a bug
that seems to happen after multiple save : the VHDL additional
property was deleted *before* the full hierarchical dump was
finished.
Now, we save each Cell only once so it does not occur, but
should make a deeper investigation later.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), the RoutingPads
for the input and output of the buffer where sometimes put too
close from each others, giving the pitch of the vertical tracks.
Now shift one pitch left the vertical branchs of the H-Tree.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), also shift down
one pitch the horizontal branch, due to track rounding they *may*
end up on the same track, generating a short.
* Change: In cumulus/plugins/core2chip, instead of the user providing
an explicit mapping towards the harness I/O pins, we expect that
the core block must have I/O pins with names matching thoses of
the harness. That way, connections are automatically made.
* Change: In cumulus/plugins/block/htree, if the root signal of the
H-Tree is a bit from a vector (like "io_in(0)"), then remove the
vector index notation on all the stem name of all the sub-nets.
Done by the unbitify() function: "io_in(0)" => "io_in_bit0".
* Change: In AnabaticEngine::setupPrerouteds(), take into account the
number of Pins. Now consider a net containing multiple Pins and, at most,
one segment as *non-routed".
This case may specifically happens for nets with pins on the north
and east side, which are slightly *inside* the abutment box (to be
seen by the router) and draw with them their *outside* direct
connection wire.
* Bug: In cumulus/plugins.chip.CoreWire, no longer put the north or
east side external Pin *exacyly* on the abutment box but *one pitch*
inside so they are correctly seens by the P&R (must be *inside*
the area of a GCell).
It is now possible to automatically nest a core block inside a harness
frame, like we do for an ordinary chip whith I/O pads. The DEF harness
file "user_project_wrapper.def" must be made available though the block
configuration variable:
conf.cfg.harness.path = './user_project_wrapper.def'
A first small example is given in:
alliance-check-toolkit/benchs/counter/sky130_c4m
The harness layout is stripped from it's native power grid (but keep
the power ring). I/O pad information in block/configuration is
slightly "bent* to manage pins instead of complete I/O pads.
* Bug: In cumulus/plugins.block.Block.setupAb(), the routingBb was not
set up when working in chip mode. Now set (to the corona AB).
* Change: In cumulus/plugins.chip.__init__, move there the CoreWire
class (from chip/pads.py) so it can be shared with the harness
version of pads.py.
* Change: In cumulus/plugins.chip.powerplane, compute the intersection
between the vertical supply stripes and the deep horizontal power
lines in a smarter fashion, so two (or more) vertically contiguous
BigVias are merged into one (two BigVia side by side where causing
mimimal spacing distance violation on the cut in Sky130).
* New: In cumulus/plugins.block.congiguration: New PowersConf config
sub-object to store characteristics of the "powmid_x0" cell.
The name of the Cell with which to build the vertical power
rails is given though the cfg parameter:
"cfg.etesian.cell.power"
* New: In cumulus/plugins.block.spares, add support for creating
vertical power lines along with the buffers pools of the H-Trees.
At most, one vertical power rail will be put exactly at the right
edge of the buffer pool of each leaf QuadTree. We can reduce that
number, using the parameter:
"cfg.block.vRailsPeriod = N"
Which give the ratio to use (one over N QuadTree leaf).
WARNING: This may not work if the QuadTree is "dented" not in a
corner but in the *middle* of the side. Needs to be
improved and/or checked.
* New: In AnabaticEngine::printMeasures(), re-enable runtime & memory
footprint in measurements.
* Bug: In Anabatic::AutoSegment CTOR, correct computation of the initial
number of global segments. We were relying on the "global" flag,
which is *not* set at this stage. Now compare source and target
GCells.
* New: In KatanaEngine::runGlobalRouter(), store H-ovE & V-ovE in
measurements.
* New: In KatanaEngine CTOR, add the number of gates (flattened) to
the measurments.
* New: In KatanaEngine::runNegociate(), add the number of GCells to
the measurements.
* Change: In KatanaEngine::printCompletion(), compute the wirelengths
in either lambdas (symbolic) or *nanometers* (real).
* New: In cumulus/plugins.block.Block, add a setting to request the
Katana measurements dumping: "cfg.katana.dumpMeasures"
* Change: In cumulus/plugins.block.HTree._rrouteHTree(), make the
non-routing of the root net the default policy. Straight routing
can still be activated with the use of Spares.ROUTE_ROOT_NET.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), on the top level
H-Tree, draw a wire to the north side of the abutment box *only*
if the root (usually clock) signal is *external*. It may be that
it is *internal*, so must be routed as a normal one to the root of
the tree.
* Bug: In cumulus/plugins.block.htree._connectLeaf(), when HEAVY_LEAF_LOAD
was used, the additionnal horizontal segment added to connect the
extra buffer may have been:
1. Misaligned, causing the blockage to be wrongly taken into account
and leading to potential short circuits.
2. In some RoutingGauge configurations, the extra length added to
the segment left extention was too short, leading to DRC violations.
So created new GaugeConf methods to manage thoses problems:
* GaugeConf.getStackX() & GaugeConf.getStackY() to get back the
contact coordinates of the *deep* part (typically the METAL2).
So be able to align on them.
* GaugeConf.createHorizontal(), added a parameter to explicitely
state the additional length of the *left* extension. This is lazy,
will soon add both.
* Change: In Cumulus/plugins.block.Block, for standalone block,
the external Pin where created non-square, the "perpandicular"
side made a half wire width. But in case the wire width was an
odd number of physical grid, it was leading to offgrid screaming
in the GDS driver.
Now, just make them square...
The CMake version set was so old that obsolete policies were being
enabled and breaking FindPython. 2.8 should still be old enough not to
cause problems for any current users.
Signed-off-by: Myrtle Shah <gatecat@chipflow.io>
large enough instead of creating one big via along the horizontal
cell power lines, we create one big VIA at each end. To avoid to
create too massive obstructions.
But the thresold was too high for cmos45, leading to short with
the clock tree trunk.
* Bug: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
The minimal length of the segment intermediate wires where computed
for the minimal area using an integer division ( // ), which is
stupid for less than 1.0 values. They are real quantities at this
point...
This was making the DRC of ls180 failing.
* New: Python/C++ API level:
* Write a new C++/template wrapper to get rid of boost::python
* The int & long Python type are now merged. So a C/C++ level,
it became "PyLong_X" (remove "PyInt_X") and at Python code
level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
* Configuration is now integrated as a Hurricane component,
makes use of the new C++/template wrapper.
* vlsisapd is now defunct. Keep it in the source for now as
some remaining non essential code may have to be ported in
the future.
* Note: Python code (copy of the migration howto):
* New print function syntax print().
* Changed "dict.has_key(k)" for "k" in dict.
* Changed "except Exception, e" for "except Exception as e".
* The division "/" is now the floating point division, even if
both operand are integers. So 3/2 now gives 1.5 and no longer 1.
The integer division is now "//" : 1 = 3//2. So have to carefully
review the code to update. Most of the time we want to use "//".
We must never change to float for long that, in fact, represents
DbU (exposed as Python int type).
* execfile() must be replaced by exec(open("file").read()).
* iter().__next__() becomes iter(x).__next__().
* __getslice__() has been removed, integrated to __getitem__().
* The formating used for str(type(o)) has changed, so In Stratus,
have to update them ("<class 'MyClass'>" instead of "MyClass").
* the "types" module no longer supply values for default types
like str (types.StringType) or list (types.StringType).
Must use "isinstance()" where they were occuring.
* Remove the 'L' to indicate "long integer" (like "12L"), now
all Python integer are long.
* Change in bootstrap:
* Ported Coriolis builder (ccb) to Python3.
* Ported Coriolis socInstaller.py to Python3.
* Note: In PyQt4+Python3, QVariant no longer exists. Use None or
directly convert using the python syntax: bool(x), int(x), ...
By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
* In order to compile user's must upgrade to my own rebuild of
PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
buffer of the H-Tree to the original signal (mainly: top clock).
Strangely, it was only done when working in full chip mode.
In the LS180, probably due to the implementation of a small RAM
with DFFs, some leaf of the clock tree (H-Tree) got heavily
loaded (around 80 DFFs sinks). Implement an option that allow
the leaf of the QuadTree to use three buffers instead of one.
The sinks are partitionned using their angle from the center
of the leaf (trigonometric direction). CChoose the bigger angle
gaps to perform the split.
* Change: In Cumulus/plugins.block.configuration.GaugeConf, in
getNearestHorizontalTrack() and getNearestVerticalTrack() add an
offset argument to shift the position of the requested track
by a certain amount.
* Change: In Cumulus/plugins.block.configuration.GaugeConf, in
createHorizontal(), add a flag to make the source end of the
segment to "stick out". Useful when connecting to a stacked
VIA top, but using a lower layer that can be shifted.
* New: In Cumulus/plugins.block.spares.Spares, BufferPool & QuadTree,
add support for selection and management of multiple buffers at
the same time. Basically returns a list of selected buffer
instances instead of just one instance.
Added HEAVY_LEAF_LOAD flag to Spares. To be used by all tools
classes that makes use of it.
Added QuadTree.runselect(), be sure to call it between different
H-Tree operations, otherwise results will be strange.
* New: In Cumulus/plugins.block.htree.HTree, in case of heavy leaf
load, in the leaf of the tree, allocate three buffers instead
of one. Select them to form a triangle around the main one.
That is, use (i,j), (i+1,j) and (i,j+1).
Added a HTree._connectLeaf() to share the handling of the child
buffer connexions. Whether they are leaf of not and heavy or not.
* Change: Cumulus/plugins.block.Block, expand HTree support to
manage the HEAVY_LEAF_LOAD flag.
* In Cumulus/plugins/block/macro.py, the METAL3 blokage was too narrow
on the left side, allowing use of METAL3 track too close from
internal components.
The METAL5 blockages around jumpers where also too narrow.
Thoses problems where seen with the density filler which put
wires everywhere.
* Change: In Etesian::Slice::fillHole(), instead of cramming the home
with tix_x0 only, put one tie at both ends and fill the rest
with fill_x0. This should help the vendor density filler to
equalze.
* New: In Etesian::Configuration, add the parameter:
"etesian.tieName" (for tix_x0) as it now separate from the simple
filler cells.
* Bug: In cumulus/plugins.chip.libresocio, the ioPadInfos where inverting
"d" and "s" terminals on IOPadInOut. This was indirectly detected by
the DRC complaining about floating gates on the "d" connected nets!
* New: cumulus/plugins.checks, plugin providing a oneDriver() function
to check that each net has one and only one driver. This is for
Cell that are not P&R (in which it is also checked). So, typically
the chip level.
* New: In cumulus/plugins.chip.core2chip, add a call to oneDriver().
* Bug: In cumulus/plugins.chip.core2chip, clear Spice extensions after
save. Otherwise we may use an outdated Spice extension after the
P&R. This is were Net missing Spice::Bit may occur.
The structure of the driver is copied from the Vhdl one. It is not
integrated as a an AllianceFramework one but as a standalone like
GDS. For now use numerical indexes for electrical nodes but also
support strings. The nets are ordereds in reverse alphabetical
order, but a custom order can be defined, if we read the model
from an external SPICE subckt (to be done).
SPICE saving has also been added to the cumulus/rsave plugin
and the block/chip P&R one.
* Change: In cumulus/plugins.chip.chip.doConnectCore(), do not use the
feature of the HTree to connect the root buffer straight to the
corona pin. It prevents the router to insert a diode when those
wires are too long. So let the standard router manage them.
Should add diode insertions in HTree.connectHTrees() later.
* Bug: In cumulus/plugins.chip.powerplane.Builder._connectHTree(),
when building the stacked VIAs over the corona Pin and the
root buffer RoutingPad, pass the GaugeConf.HAccess flag so the
stack stops at METAL4 (top horizontal layer).
Before we where also adding a VIA up to METAL5 which was unused
and caused a minimal area violation.
* Change: In cumulus/plugins.block.macro, the METAL2 blockage was
allowing horizontal tracks to be used but the METAL3 blockage
was conflicting with the end of the perpandiculars.
The router was not able to manage that, so we slightly expand
the METAL2 blockage to encompass the unreachable track.
For the same reason, add a METAL4 blockage over METAL2.
* New: In cumulus/plugins.chip.pads, add METAL5 jumpers on all wires
going to/from the I/O pads on the East & West side. This is a
quick hack as:
1. We should put it also on North/South, but no violation
happens here.
2. We should put it on *ouput* wire only (for only those are
connected to transistors gates).
* New: In cumulus/plugins.chip.macro, put jumpers on the East side
connectors for the SRAM block. Also a quick hack, not robust for
anything else than the SRAM.
* Change: In cumulus/plugins.Block.getLeafUnder(): formerly, we where
using the cut-lines (x/y) to locate which leaf a point is under.
But in case of incomplete tree, it is difficult to manage.
Now we chosse the leaf according to the distance to the center
of the leaf area. Choose the shorter, of course.
This solve the H-Tree DFF bad assignment around the PLL (top
right corner) in LS180.
* Bug: In Cumulus/plugins.block.Block, re-order Etesian tool creation
and virtual net flattening. Must investigate later why it is so
sensitive to at least warn/stop cleanly.
* Bug: In Cumulus/plugins.chip.powerplane.Builder._connectHTree(), is was
previously assumed that a net manged by a H-Tree was always coming from
the outside (i.e. a clock or a reset signal).
It is no longer the case, for example with the PLL internally generated
clock.
So prune internal signals in this method.
The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.
* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
of the function to allow the user to select nets that will *not*
be flattened. This makes the NoClockFlatten flag effectively obsolete,
we keep it for backward compatibility.
The net names can be of non top level ones. In that case, they must
use the name an HyperNet will get (the Occurrence name). For example:
"instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
new utility function pyListToStringSet() to translate a Python list into
a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
from the flattening procedure. Those excluded nets will also be
excludeds from the Coloquinte nets *and* HFNS synthesis, as they
are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
on nets that are already fixed or detaled route. This replace the
clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
of clock-tree by the more generic H-Tree. That is, we can ask the P&R
to create H-Tree on any net of the design, not only the ones matcheds
as clock. The net does not even need to be top-level.
This is to manage the PLL internal clock generated by the PLL in
the LS180 chip.
Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
there was an inversion of the H & V routing gauges to compute the
track into which put the H-Tree center to corona edge wiring.
This was causing tracks to be used twice, seen in the ao68000 test
bench.
* Bug: In cumulus/plugins.macro.Macro.__init__(), stick out the rigth number
of pitches on North & East sides (never tested before).
* New: In cumulus/plugins.macro.Macro.__init__(), manage layer change
if the terminal is not in the preferred routing direction. Use BigVia
and put at least two cuts.
* Bug: In cumulus/plugins.chip.Chip.save(), now completely delegate the
saving procedure to the base class (i.e. Block.save() which is
BlockConf.save()).
* Bug/Change: In cumulus/plugins.block.configuration.BlockConf.save(),
Now manage all the configutation, whether it is a simple block or
a whole chip.
In the case of a whole chip we must force the saving on both
chip and corona as the later, being P&R will be seen as a terminal
block and not recursively saved.
* In cumulus/plugins.block.Block.{place,doPnr}(), reorder the
feed insertion and spare buffer deletion call. Formerly, we
were :
1. Creating spare buffersa (Python).
2. Placing (C++)
3. Adding feeds (EtesianEngine::toHurricane() call) (C++).
4. Removing unused spare buffers (Python).
So, step 4 was *not* informing the C++ placement data-structure
created at step 3 of the change. Resulting in occurrences using
deleted Entities (Instance).
Now we swap step 3. and 4. so toHurricane() is called *after*
any Python managed change is done.
Ideally, what we should implement is a way for Python to inform
the C++ data-structure. No real problem here, but time...
* Change: In cumulus/plugins.block.configuration.Configuration.save()
and cumulus/plugins.chip.Chip.save(), according to the kind of
routing gauge we are using (symbolic or real), either recursively
save all the layouts (AP symbolic files) or only the top-level
GDSII (which embed all the hierarchy) one.
* Bug: In cumulus/plugins.chip.pads, we were connecting the ground and
power supplies to all the horizontal wires in the corona ring.
But, when there are more than one and especially at the outer
border of the pad, the vertical connecting wire will create
various shorts over the pad.
Now we connect only to the innermost horizontal wire only.
Had to chech if the core side of the pad is north or south.
* Bug: In cumulus/plugins.chip.powerplane, while building the connexion
from the corona border to the root of the HTree, the horizontal
wire at the top was too close from the border causing a minimal
spacing error in the DRC. Now put two tracks of distance.
* Bug: In cumulus/plugins.block.block.py, always import Python modules
using the exact same path. Otherwise the module may get imported
twice and static variables are duplicated, generating a big mess.
This was causing problem for the LUT in macro.py, and got SRAMs
blocks encapsulated twice.
* New: In cumulus/plugins.block.block.Block.addPlaceHolder(), create
a "place holder" instance over a given area to prevent the placer
from using it. Allow to make space reservation.
* New: In cumulus/plugins.block.configuration.BlockConf, copy the
toXPitch() and toYSlice() methods from spare in order to share
them between modules. Still have to remove some other local copies.
* New: In cumulus/plugins.block.spare.QuadTree, keep a list of all
the X centers of the partitionned areas. For yse by the power lines.
* New: In cumulus/plugins.chip.chip, move doPowerLayout() call from
doChipFloorplan() to doConnectCore(), this is to delay the call
until *after* the spare QuadTree has been created and we can
align the power lines to the centers of the QuadTree.
* New: In cumulus/plugins.chip.pads.Corona.doPowerLayout(), if a
spare QuadTree has been created, align the power lines on the
X center of the leaf areas. This is a cheap way to avoid DRC
errors between the power BigVias and the wires from the various
clock trees (on METAL5).
* New: In cumulus/plugins.block.macro, add an ad-hoc patch for Staf's
SRAMs. The blockage areas are slightly too narrow. We enlarge
them by one pitch.
* Change: In Cumulus/plupins.chip.pads.Side, in some case (LibreSOCIOPads),
when not put side by side, the I/O pads must be separated by a
minimal distance.
Introduce the new configuration parameter:
cfg.chip.minPadSpacing
Disabled if zero or non-defined.
Fix NWELL DRC errors for TSMC.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
the external status of the former Net. When a Net::merge() is
performed, we must keep track of whether the merged (destroyed)
one was external and keep that information.
Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
search of the net name in *internal* aliases. Otherwise only the
aliases tagged as *external* will be searched.
It was a bug that, when looking for a Plug master net by name
we got an homonymous internal net. In that case we must only
look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
unvectorize it, like when it is non-contiguous (we use the
isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
a flag UniquifyUpperCase to uniquify the names in uppercases.
In case of a clash with the same name in lowercase.
Prepend 'u' before all previously uppercased letter. For
example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
The Catalog flags is exported to Python for use by the blif2vst
script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
a new gate each time it is called instead of making just one for
each Model. This way, if two outside nets are connected to one
or zero they do not get merged (should work, but will be less
clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
master net in the instances models (by name), limit the search
to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
(i.e. components) with 'cmpt_' to avoid clash names with signals
in VHDL.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.rpAcces(), start
building the stack of contacts + short segments straps from the
layer of the RoutingPad and *not* from the first layer of the
RoutinhGauge.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.setStackPosition(),
Only align in the RoutingLayer gauge direction of the top layer of
the stack. For example, METAL2(H) will be y aligned or METAL3(V)
will be x aligned.
* Bug: In Cumulus/plugins.chip.powerplane.Builder._connectClock(),
forgot to call expandMinArea() on the pinRp contact stack.
* Change: In Cumulus/plugins.block.spares, allow the QuadTree to have
only *some* of it's four childs (BL, TL, TR, BR).
Modify QuandTree.getLeafUnder() so when there is no leaf under
the point, due to an incomplete tree, we get the closer leaf.
Leaf are suppressed when their center points (where the buffers
are to be put) are under a FIXED Instance (that is, an opaque block).
Those opaque blocks (or macro blocks) must be put *on the periphery*
of the design, because the closer they got to the center, the larger
the chunks of QuadTree that are removeds.
* Change: In Cumulus/plugins.block.clocktree, based on the spare
QuadTree changes, can now build a clock-tree with some of the
leaf missing. Should find a way to compensate for the missing
leaf wires & buffer (dummies).
* New: In Cumulus/plugins.block.matrix.RegisterMatrix, based on pattern
matching the output of DFF, allow to rebuild and place a matrix of
DFF constituting a RAM.
It finally proven not useful because it is a too naive approach.
Intermediate gates (buf_x2) must be found too. Most of the control
signals have more than 20 sinks so gets splitted by HFNS and lastly,
we would want the decoder to be integrated too, but they are not
regulars.
The right way to do it is to create a generator that build it
then expose it in a way nMigen can understand (not the other way
around, nMigen -> Yosys).
* New: CRL::restoreNetsdirection() (in ToolBox) that checks the coherency
of all Nets direction through a complete hierarchy of cells.
Stops at Cells flagged "TerminalNetlist".
Directions are rebuilt for all the Cells part of the hierarchy
in a bottom up fashion. It is also checked that Nets have only one
driver (we assume there is no three-state busses).
To sort cells in hierarchical order (bottom up according to their
depth), copy the DepthOrder class from the GDSII driver. Will unify
them later.
exported to the Python interface.
* New: In cumulus/tools/blif2vst.py, add a call to restoreNetsdirection()
before saving.
Jean-Paul Chaput
Myrtle Shah
Luke Kenneth Casson Leighton