In CoreToChip, the "iolib" I/O pad library an alternative to the "cmos"
one. "cmos" uses the pxlib library while iolib uses a symbolic abstract
version of the C4M (real) I/O pad.
The initialization is a bit split as the "cmos" library are part of
Alliance, while "iolib" is in alliance-check-toolkit. So "iolib" is
added at designflow.technos.setupCMOS().
Setup additional configuration parameter directly in:
core2chip.niolib.CoreToChip.__init__().
* Bug: In CRL/technos.node180.gf180mcu_c4m.iolib.py, remove the VDD and
VSS ring terminals in the pad as only *some* of the have it.
Assume that it is a bug from GF. The power rail will still be ok
as it connect by abutment (with the filler & other I/O pads).
* New: In cumulus.plugins.block.configuration.py, added support for
iterable I/O pad specifications in ioPads argument.
* New: In cumulus.plugins.core2chip.core2chip.py, add support for
any number of control signals on I/O pads. Not fully implemented
yet, as we only allow to hard-wire them either to one or zero.
Raise an error if _connect() fails to find a master net, so
we don't fail strangely later...
* New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin
for Yosys.
* Fix: In designflow.svase, remove the transient file "slang-args.txt".
* Change: In designflow.yosys, remove the direct SystemVerilog support
that is delegated to Surelog and just load the resulting UHDM.
Merge with yosysnp and automatically detect if we can load the
Python plugin or go through a script.
* New: In designflow.yosys, add support to load SystemVerilog with the
synlig plugin (CHIPS Alliance).
Integrate back the "non-Python" version of the task. Now switch
automatically between Python & Non-Python based on the availability
of the plugin. Also select between "yosys" & "yowasp-yosys".
* Change: In svase & sv2v, suppress the requirement of the *first*
dependency file to be used as the default target. Now use the
"top module" argument.
* Bug: In cumulus.plugins.chips.pads.Side._placePads(), when pads have
positions they must be reorder *prior* to recomputing the pad
final position? In order to avoid overlap and ensuring that they are
on pitch, according to the I/O pad routing gauge.
* Change: In Katana::PowerRailsPlanes::Rail::doLayout(): change the delta
computation. Extend of the pitch *minus* the half wire-width *minus* 1.
So a wire at minimal with will reach exactly the previous and next
track axis. And will not be insterted in them due to the "minus 1".
TrackFixedSegments created at this stage must be flagged as
TElemBlockageNet, so that any overlap between them is not seen as an
error by the track overlap checker.
This was a problem for the clock tree wires which partly uses
pre-fixed wires, but the driver of the H-Tree is a normal signal that
must abide the usual checking.
* Change: In Katana::TrackFixedSegment::getNet(), no longer rely on the
kind of net to choose to return the actual net or the blockage one,
but uses the TElemUseBlockageNet flag.
Formerly, the H-Track could be shifted *relative* to the position of
the center of the RoutingPad. Which may become fragile in case of a
change in the standard cell library. So we create a new feature allowing
to specify the H-track as an offset *from the bottom of the slice*.
Two offset can be specified:
* spares.htreeOffsetDriver : for the main H part, connected to the
driver.
* spares.htreeOffsetSink : for the small parts connecting to every
fours sinks of the tree.
This to avoid those two to overlap. The sink of the "N" stage with
the driver of the "N+1" stage (so input & ouput of the same buffer).
* Change: In cumulus.plugins.core2chip.CoreToChip, add new methods:
* hasCornerCell() (return False)
* hasFillerCells() (return False)
* getCornerCell() (raise NotImplementedError)
* createSpacer() (raise NotImplementedError)
* createCorner() (raise NotImplementedError)
Those methods needs to be overloaded in derived classes when I/O spacers
and corner cells are supplied.
In IoPad, add a NON_CONNECT case for dummy pad that are not connected.
* New: In cumulus.plugins.chip.pads, delegate spacer & corner creation to
the coreToChip concrete class.
* New: In cumulus.plugins.block.configuration.IoPadConf, add support for
non-connected (dummy) pads.
Formerly, CoreToChip was seen as building the top-level netlist of the
chip only. But, when using special spacer pads, we need to have access
to that specific information from inside the Chip pads builder.
So we now move CoreToChip as an internal part of Chip. The right
CoreToChip to use (techno dependant) must be given as a configuration
parameter:
"conf.coreToChipClass"
It is the class, not an object that must be suplied.
* Change: In cumulus.block.configuration and cumulus.block.htree, two new
configuration parameters allow to specify the offset of the horizontal
branch of the H-Tree manually:
cfg.spares.htreeRootOffset (first level of the tree)
cfg.spares.htreeOffset (subsequent levels)
The offset is given in number of tracks.
Formerly we were using Placement::Area::TrackAvoid() to shift cells terminals
out of the way of the reserved vertical track. With double height cells,
this is coming more complex and due to heavy tracks uses in some cells,
the shift required may becomes too great. Instead, we place filler cells
just underneath the reserved track to prevent their usage. This is a
supplemental constraint on the router, but the new version manage it
correctly.
* New: In cumulus/block.spares.Spares.trackAvoid() to place filler cells
under a given vertical area.
* New: In LefImport::LefParser, add support for LEF Polygons that are
translated into Hurricane Rectilinears.
* Change: In LefImport::setMergeLibrary(), the default behavior for the
LEF parser is to create a new separate library under LEF/<lib_name>
for each file. But if the various cells are put each one in it's own
cell, this is suitable. So we can now set a library beforehand into
which they will be all put.
* New: in CRL/technos.node180.gf180mcu, configuration files for the
GF180MCU open PDK.
* New: in cumulus/designflow.technos, added a setupGF180MCU_GF() to
initialize the GF PDK.
* In cumulus.designflow.technos.setupCMOS(): export back the guessed
ALLIANCE_TOP *before* importing technos.symbolic.cmos so it is
used for the CELLS_TOP. This avoid defaulting to /soc/alliance
which does exists only on LIP6 computers...
* New: In cumulus.designflow: add yosysnp to manage Yosys without
Python support enabled.
Add klayout support for running scripts in batch mode.
Add generic system command support.
* Change: In cumulus.designflow.task.TaskFlow, systematically
convert pathes (str) into pathlib.Path in targets and depends.
* New: In cumulus.designflow.clean.Clean, add cleaning by glob.
* Change: In cumulus/plugins/__init__.py, new behavior for loading
plugins supplied as third party. In order to avoid messing up
with the "site-packages/coriolis/" main package tree (with
modules named "coriolis.<MODULE>", they have to be under
"site-packages/addons/coriolis/" (so modules will be named
"addons.coriolis.<MODULE>"). This should prevent *overwritting*
standard modules by third party ones.
Now uses pathlib for module loading.
Had a conflict between Hurricane.Path and pathlib.Path, now do
not import the Hurricane one into the module globals...
* Move all Python stuff under a common Python namespace "coriolis".
* Instead of having a series subtrees for each tool, integrate
everything in one common tree. So now, all components can be
located either with an absolute path from "coriolis" or, inside
cross-reference themselves through relatives imports.
* As a consequence, we only need to add ".../site-packages/coriolis/"
to the PYTHONPATH, and not a whole bunch of subdirectories.
And nothing, if installed in-system.
* The tree of free technologies configuration files is also moved
below "coriolis/technos" instead of "/etc".
* Supressed "cumulus" level for the plugins.
* All python modules are rewritten using relative imports except
for the configuration files that uses absolute import as they
can be cloned outside of the tree to serve as templates.
* Change: In boostrap/FindPythonSitePackages, include "/coriolis" in
Python_CORIOLISARCH and Python_CORIOLISLIB.
Provide a Python_SITELIB *without* "/coriolis" appended.
* Change: In cumulus/plugins/__init__.loadPlugins(), must prefix modules
read in the plugins directory by "coriolis.plugins.". No longer need
to add their path to sys.path.
* Change: In crlcore/python/technos/nodeX/*/devices.py, the scripts of
the layouts generators must be prefixed by "coriolis.oroshi.".
* Change: In CRL::System CTOR, no longer add the pathes of the various
plugins to sys.path. Only "site-packages/coriolis/".
* New: In Utilities::Path::toPyModePath(), new method to convert a
filesystem path into a python module path.
Examples:
"coriolis/plugins/block" --> "coriolis.plugins.block".
"coriolis/plugins/rsave.py" --> "coriolis.plugins.rsave".
* Change: In katanaEngine::_runKatanaEngine(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In BoraEngine::_runBoraEngine(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In UnicornGui::_runUnicornInit(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In cumulus.plugins.chip.constants, put the constants
outside __init__.py to avoid a loop at initialization.
* New: In cumulus/block.bigvia, add a getBoundingBox() method.
* New: In cumulus/block.configuration.GaugeConf.rpAccess(),
add a vertical strap segment in case the RP is not high enough to
accomodate the potential offset of the contact.
In case of gauge with only two routing layers, if the RP
is vertically accessed, do not put a VIA12 but just a METAL2
contact (there will be *no* turn).
* Change: In cumulus/chip.CoreWire.drawWire(), the wire at *chip level*
going to the pad was shrunk of 3 pitch when *not* in the preferred
routing direction. Removing it as it creates gaps in some cases.
This was likely needed for a specific kind of I/O pad so should
be re-enabled on targeted cases in the future.
* Change: In cumulus/chip.corona.VerticalRail, manage in a smarter way
the conflicts when a rail is accessed from both sides overlapping
on an Y position. That is, from the supply I/O pads *and* from the
*core* supply lines.
Formerly, we just didn't connect the core power line, which was
a mistake potentially leaving power rails unconnected (it it did
occur on both sides).
Also checks if the conflict really arise, that is, the power lines
are both on top or bottom.
* Change: In cumulus/chip.pads.Side._placePad(), manage I/O pads with
a bottom left corner of abutment box *not* at (0,0). Argh!
* Bug: In cumulus/chip.pads, create the filler pad instances in the
chip, not in the corona.
* Change: In cumulus/plugins.chip.configuration, do not add an extra
slice height to the minHCorona & minVCorona. Now seems a bit overkill
on small chips.
Jean-Paul Chaput
Robert Taylor
Gabriel Gouvine