In cumulus, integrate CoreToChip inside Chip.

Formerly, CoreToChip was seen as building the top-level netlist of the
chip only. But, when using special spacer pads, we need to have access
to that specific information from inside the Chip pads builder.
So we now move CoreToChip as an internal part of Chip. The right
CoreToChip to use (techno dependant) must be given as a configuration
parameter:

  "conf.coreToChipClass"

It is the class, not an object that must be suplied.
This commit is contained in:
Jean-Paul Chaput 2023-07-26 18:01:07 +02:00
parent a8d0371990
commit 0bd39fa839
4 changed files with 17 additions and 1 deletions

View File

@ -1411,6 +1411,7 @@ class BlockConf ( GaugeConf ):
self.katana = None
def _postInit ( self ):
trace( 550, ',+', '\tblock.configuration._postInit()\n' )
self.cfg.apply()
self.bufferConf = BufferConf( self.framework )
self.constantsConf = ConstantsConf( self.framework, self.cfg )
@ -1420,6 +1421,7 @@ class BlockConf ( GaugeConf ):
self.ioPins.append( IoPin( *ioPinSpec ) )
for line in range(len(self.ioPadsArg)):
self.chipConf.addIoPad( self.ioPadsArg[line], line )
trace( 550, ',-' )
@property
def isCoreBlock ( self ): return self.chip is not None

View File

@ -61,6 +61,17 @@ class Chip ( Block ):
self.conf.validated = False
return self.conf.validated
def doChipNetlist ( self ):
"""
Build the netlist at chip-level around the ``core`` block. Needs the ``conf.coreToChipClass``
configuration parameter to be set up. Otherwise assume the netlist is already a chip.
"""
if not hasattr(self.conf,'coreToChipClass'):
print( WarningMessage( 'Chip.doChipNetlist(): No "conf.coreToChipClass" defined, assume we already have a chip-level netlist.' ) )
return
self.conf.coreToChip = self.conf.coreToChipClass( self.conf )
self.conf.coreToChip.buildChip()
def doChipFloorplan ( self ):
self.padsCorona = None
minHCorona = self.conf.minHCorona

View File

@ -112,6 +112,7 @@ class ChipConf ( BlockConf ):
self.chipLogos = []
self.minHCorona = 0
self.minVCorona = 0
self.coreToChip = None
trace( 550, '-' )
@property

View File

@ -259,6 +259,8 @@ class IoPad ( object ):
TRI_OUT = 0x0008
ANALOG = 0x0010
UNSUPPORTED = 0x0020
FILLER = 0x0040
CORNER = 0x0080
@staticmethod
def directionToStr ( direction ):
@ -517,7 +519,7 @@ class CoreToChip ( object ):
.format( core.getName() )
] )
conf = block.state
conf._postInit()
#conf._postInit()
self.conf = conf
self.conf.useHarness = False
self.ringNetNames = []