Support for gf180mcu native I/O pads.
* Bug: In CRL/technos.node180.gf180mcu_c4m.iolib.py, remove the VDD and
VSS ring terminals in the pad as only *some* of the have it.
Assume that it is a bug from GF. The power rail will still be ok
as it connect by abutment (with the filler & other I/O pads).
* New: In cumulus.plugins.block.configuration.py, added support for
iterable I/O pad specifications in ioPads argument.
* New: In cumulus.plugins.core2chip.core2chip.py, add support for
any number of control signals on I/O pads. Not fully implemented
yet, as we only allow to hard-wire them either to one or zero.
Raise an error if _connect() fails to find a master net, so
we don't fail strangely later...
This commit is contained in:
Jean-Paul Chaput
parent
4420da664e
commit
9274c21c14
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@ -181,7 +181,7 @@ def _routing ():
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cfg.katana.globalRipupLimit = 5
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cfg.katana.globalRipupLimit = [1, None]
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cfg.katana.longGlobalRipupLimit = 5
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cfg.chip.padCoreSide = 'South'
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cfg.chip.padCoreSide = 'North'
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# Plugins setup
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cfg.clockTree.minimumSide = u(5.04) * 6
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cfg.clockTree.buffer = 'gf180mcu_fd_sc_mcu9t5v0__clkbuf_2'
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@ -99,6 +99,10 @@ def _routing():
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)
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af.addCellGauge(cg)
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af.setCellGauge('StdCell3V3Lib')
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lg5 = af.getRoutingGauge('StdCell3V3Lib').getLayerGauge( 5 )
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lg5.setType( CRL.RoutingLayerGauge.PowerSupply )
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env = af.getEnvironment()
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env.setRegister( '.*sff.*' )
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# Place & Route setup
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with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg:
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@ -162,17 +166,8 @@ def _routing():
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cfg.katana.globalRipupLimit = 5
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cfg.katana.globalRipupLimit = [1, None]
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cfg.katana.longGlobalRipupLimit = 5
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cfg.chip.padCoreSide = 'South'
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# Plugins setup
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with CfgCache(priority=Cfg.Parameter.Priority.ConfigurationFile) as cfg:
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cfg.viewer.minimumSize = 500
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cfg.viewer.pixelThreshold = 10
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cfg.chip.block.rails.count = 5
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cfg.chip.block.rails.hWidth = u(2.68)
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cfg.chip.block.rails.vWidth = u(2.68)
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cfg.chip.block.rails.hSpacing = u(0.7)
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cfg.chip.block.rails.vSpacing = u(0.7)
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cfg.clockTree.minimumSide = l(600)
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cfg.clockTree.buffer = 'buf_x1'
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cfg.clockTree.placerEngine = 'Etesian'
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@ -27,8 +27,9 @@ def _routing ():
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cfg.chip.block.rails.vWidth = u(30.0)
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cfg.chip.block.rails.hSpacing = u( 6.0)
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cfg.chip.block.rails.vSpacing = u( 6.0)
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cfg.chip.padCorner = 'gf180mcu_fd_io__cor_5lm'
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cfg.chip.padSpacers = 'gf180mcu_fd_io__fill10_5lm,gf180mcu_fd_io__fill5_5lm,gf180mcu_fd_io__fill1_5lm'
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#cfg.chip.padCorner = 'gf180mcu_fd_io__cor'
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#cfg.chip.padSpacers = 'gf180mcu_fd_io__fill10,gf180mcu_fd_io__fill5,gf180mcu_fd_io__fill1'
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cfg.chip.padCoreSide = 'North'
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af = AllianceFramework.get()
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cg = CellGauge.create( 'LEF.GF_IO_Site'
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, 'Metal2' # pin layer name.
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@ -57,7 +58,6 @@ def _loadIoLib ( pdkDir ):
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print( ' o Setup GF180MCU I/O library in {}.'.format( ioLib.getName() ))
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io.vprint( 1, ' o Setup GF180MCU I/O library in {}.'.format( ioLib.getName() ))
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cellsDir = pdkDir / 'libraries' / 'gf180mcu_fd_io' / 'latest' / 'cells'
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print( cellsDir )
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for lefFile in cellsDir.glob( '*/*_5lm.lef' ):
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print( lefFile )
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gdsFile = lefFile.with_suffix( '.gds' )
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@ -65,6 +65,12 @@ def _loadIoLib ( pdkDir ):
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Gds.setTopCellName( gdsFile.stem[:-4] )
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Gds.load( ioLib, gdsFile.as_posix(), Gds.Layer_0_IsBoundary|Gds.NoBlockages )
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LefImport.load( lefFile.as_posix() )
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# Demote the VDD/VSS nets until we understand how that works.
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for cell in ioLib.getCells():
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for net in cell.getNets():
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if net.getName() in ('VDD', 'VSS'):
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net.setExternal( False )
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net.setGlobal( False )
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af.wrapLibrary( ioLib, 1 )
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@ -65,6 +65,7 @@
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/core2chip/niolib.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/core2chip/libresocio.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/core2chip/sky130.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/core2chip/gf180mcu.py
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)
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set ( pyPluginChip ${CMAKE_CURRENT_SOURCE_DIR}/plugins/chip/__init__.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/chip/constants.py
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@ -284,7 +284,6 @@ def setupGf180mcu_c4m ( checkToolkit=None
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cfg.misc.verboseLevel2 = True
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cfg.etesian.graphics = 3
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cfg.etesian.spaceMargin = 0.10
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cfg.anabatic.topRoutingLayer = 'metal6'
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cfg.katana.eventsLimit = 4000000
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af = CRL.AllianceFramework.get()
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lg5 = af.getRoutingGauge('StdCell3V3Lib').getLayerGauge( 5 )
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@ -15,6 +15,7 @@
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import sys
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import re
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import os.path
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import collections
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from operator import itemgetter
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from ... import Cfg
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from ...Hurricane import DataBase, Breakpoint, DbU, Box, Transformation, \
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@ -1449,7 +1450,22 @@ class BlockConf ( GaugeConf ):
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for ioPinSpec in self.ioPinsArg:
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self.ioPins.append( IoPin( *ioPinSpec ) )
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for line in range(len(self.ioPadsArg)):
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self.chipConf.addIoPad( self.ioPadsArg[line], line )
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bits = []
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if not isinstance(self.ioPadsArg[line][-1],str) \
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and isinstance(self.ioPadsArg[line][-1],collections.Iterable):
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bits = self.ioPadsArg[line][-1]
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elif isinstance(self.ioPadsArg[line][-1],int):
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bits = range( self.ioPadsArg[line][-1] )
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if bits != []:
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for bit in bits:
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spec = [ self.ioPadsArg[line][0]
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, self.ioPadsArg[line][1]
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]
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for i in range( 2, len(self.ioPadsArg[line])-1 ):
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spec.append( self.ioPadsArg[line][i].format( bit ))
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self.chipConf.addIoPad( spec, line )
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else:
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self.chipConf.addIoPad( self.ioPadsArg[line], line )
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trace( 550, ',-' )
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@property
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@ -693,11 +693,11 @@ class Corona ( object ):
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if plug.getMasterNet().isGlobal():
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net = self.conf.cell.getNet( plug.getMasterNet().getName() )
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if not net:
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raise ErrorMessage( 1, 'Corona._padAnalysis(): Ring net "%s" is not connected and there is no global net (in pad \"%s").' \
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% plug.getMasterNet().getName(), padCell.getName() )
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raise ErrorMessage( 1, 'Corona._padAnalysis(): Ring net "{}" is not connected and there is no global net (in pad "{}").' \
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.format( plug.getMasterNet().getName(), padCell.getName() ))
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else:
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raise ErrorMessage( 1, 'Corona._padAnalysis(): Ring net "%s" is neither connected nor global (in pad \"%s").' \
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% plug.getMasterNet().getName(), padCell.getName() )
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raise ErrorMessage( 1, 'Corona._padAnalysis(): Ring net "{}" is neither connected nor global (in pad "{}").' \
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.format( plug.getMasterNet().getName(), padCell.getName() ))
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if net:
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self.padRails.append( ( net
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, component.getLayer()
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@ -375,6 +375,7 @@ class IoPad ( object ):
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or self.nets[0].chipExtNetName.startswith('io_in') \
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or self.nets[0].chipExtNetName.startswith('io_out')
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if hasEnable:
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trace( 550, '\tself.nets = {}\n'.format( self.nets ))
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if len(self.nets) < 2:
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enableNet = self.coreToChip.newEnableForNet( self.nets[0] )
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self.nets.append( self.coreToChip.getIoNet( enableNet ) )
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@ -387,6 +388,7 @@ class IoPad ( object ):
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connexions.append( ( self.nets[0].chipIntNet , padInfo.inputNet ) )
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connexions.append( ( self.coreToChip.newDummyNet(), padInfo.outputNet ) )
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if hasEnable:
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trace( 550, '\tenable Pad={} <-> {}\n'.format( padInfo.enableNet, self.nets[1].chipIntNet ))
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connexions.append( ( self.nets[1].chipIntNet, padInfo.enableNet ) )
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elif (self.direction == IoPad.TRI_OUT) and (len(self.nets) < 2):
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self.nets[0].setFlags( IoNet.DoExtNet )
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@ -415,6 +417,11 @@ class IoPad ( object ):
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connexions.append( ( self.nets[0].chipIntNet, padInfo.inputNet ) )
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connexions.append( ( self.nets[1].chipIntNet, padInfo.outputNet ) )
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connexions.append( ( self.nets[2].chipIntNet, padInfo.enableNet ) )
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for controlInfo in padInfo.controlNets:
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controlNet = self.coreToChip.newControlForPad( self.ioPadConf, controlInfo )
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self.nets.append( self.coreToChip.getIoNet( controlNet ) )
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self.nets[-1].buildNets()
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connexions.append( ( self.nets[-1].chipIntNet, controlInfo.name ) )
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if not self.coreToChip.useHarness():
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self.pads.append( Instance.create( self.coreToChip.chip
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, self.padInstanceName
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@ -448,13 +455,21 @@ class CoreToChip ( object ):
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to the core actually bearing information.
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"""
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class IoControlInfo ( object ):
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def __init__ ( self, name, defaultState ):
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self.name = name
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self.defaultState = defaultState
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pass
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class IoPadInfo ( object ):
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def __init__ ( self, flags, padName, padNet, coreNets ):
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self.flags = flags
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self.name = padName
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self.padNet = padNet
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self.coreNets = coreNets
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def __init__ ( self, flags, padName, padNet, coreNets, controlNets=[] ):
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self.flags = flags
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self.name = padName
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self.padNet = padNet
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self.coreNets = coreNets
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self.controlNets = [ CoreToChip.IoControlInfo( net[0], net[1] ) for net in controlNets ]
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return
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@property
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@ -508,6 +523,10 @@ class CoreToChip ( object ):
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if not masterNetO: masterNet = instance.getMasterCell().getNet( chipNet.getName() )
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elif isinstance(masterNetO,Net): masterNet = masterNetO
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else: masterNet = instance.getMasterCell().getNet( masterNetO )
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if not masterNet:
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raise ErrorMessage( 1, [ 'CoreToChip._connect(): No net "{}" in cell "{}".' \
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.format( masterNetO, instance.getMasterCell().getName() )
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] )
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instance.getPlug( masterNet ).setNet( chipNet )
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return
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@ -571,6 +590,22 @@ class CoreToChip ( object ):
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self.dummyNetCount += 1
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return dummy
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def newControlNet ( self, controlName, constantType ):
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"""
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Create a new control signal, in *core* cell, to control the associated I/O pad.
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The control signal is tied to a constant value, either zero or one.
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:param controlName: The name of the control net *in the core cell*.
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:param constantType: Whether the control signal is set to zero or one.
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"""
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instance = self.conf.constantsConf.createInstance( self.core, constantType )
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control = Net.create( self.core, controlName )
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control.setExternal ( True )
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control.setDirection( Net.Direction.OUT )
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getPlugByName( instance, self.conf.constantsConf.output(constantType) ).setNet( control )
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self.conf.addClonedCell( self.conf.core )
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return control
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def newEnableForNet ( self, ioNet ):
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"""
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Create a new enable signal, in *core* cell, to control the associated I/O pad.
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@ -582,13 +617,16 @@ class CoreToChip ( object ):
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else:
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raise ErrorMessage( 2, 'CoreToChip.newEnableForNet(): Net "{}" is neither IN nor OUT.' \
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.format(ioNet.coreNet.getName()) )
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instance = self.conf.constantsConf.createInstance( self.core, constantType )
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enable = Net.create( self.core, ioNet.enableNetName )
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enable.setExternal ( True )
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enable.setDirection( Net.Direction.OUT )
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getPlugByName( instance, self.conf.constantsConf.output(constantType) ).setNet( enable )
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self.conf.addClonedCell( self.conf.core )
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return enable
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return self.newControlNet( ioNet.enableNetName, constantType )
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def newControlForPad ( self, ioPadInfo, ioControlInfo ):
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"""
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Create a new control signal, in *core* cell, to control the associated I/O pad.
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This is to be used for all I/O pads controls nets, save the "enable" signal.
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"""
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constantType = ConstantsConf.ONE if ioControlInfo.defaultState else ConstantsConf.ZERO
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controlNetName = '{}_{}'.format( ioPadInfo.instanceName, ioControlInfo.name )
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return self.newControlNet( controlNetName, constantType )
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def getIoNet ( self, coreNet ):
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"""
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@ -0,0 +1,248 @@
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# -*- coding: utf-8 -*-
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#
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# This file is part of the Coriolis Software.
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# Copyright (c) Sorbonne Université 2020-2023, All Rights Reserved
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#
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | C u m u l u s - P y t h o n T o o l s |
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# | |
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# | Author : Jean-Paul CHAPUT |
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# | E-mail : Jean-Paul.Chaput@lip6.fr |
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# | =============================================================== |
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# | Python : "./plugins/core2chip/libresocio.py" |
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# +-----------------------------------------------------------------+
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"""
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Core2Chip configuration for the Global Foudries 180nm I/O pad library (GF180MCU).
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"""
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import sys
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import re
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from ...Hurricane import DbU, DataBase, UpdateSession, Breakpoint, \
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Transformation , Instance , Net
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from ...CRL import Catalog, AllianceFramework
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from ...helpers import trace
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from ...helpers.io import ErrorMessage, WarningMessage
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from ...helpers.overlay import CfgCache
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from .core2chip import CoreToChip as BaseCoreToChip, IoNet, IoPad
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class CoreToChip ( BaseCoreToChip ):
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"""
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Provide pad-specific part for GF180MCU I/O pads (works in real mode).
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"""
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rePadType = re.compile(r'(?P<type>.+)_(?P<index>[\d]+)$')
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def __init__ ( self, core ):
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with CfgCache() as cfg:
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cfg.chip.useAbstractPads = False
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self.ioPadNames = { 'in' :'gf180mcu_fd_io__in_s'
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, 'bidir' :'gf180mcu_fd_io__bi_t'
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, 'analog' :'gf180mcu_fd_io__asig_5p0'
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, 'vdd' :'gf180mcu_fd_io__dvdd'
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, 'vss' :'gf180mcu_fd_io__dvss'
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, 'corner' :'gf180mcu_fd_io__cor'
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, 'spacer1' :'gf180mcu_fd_io__fill1'
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, 'spacer5' :'gf180mcu_fd_io__fill5'
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, 'spacer10' :'gf180mcu_fd_io__fill10'
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}
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BaseCoreToChip.__init__ ( self, core )
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self.ringNetNames = { 'DVDD' : None
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, 'DVSS' : None
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#, 'VDD' : None
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#, 'VSS' : None
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}
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self.ioPadInfos = [ BaseCoreToChip.IoPadInfo( IoPad.IN
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, self.ioPadNames['in']
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, 'PAD', ['Y'], [ ( 'PU' , False )
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, ( 'PD' , False )
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] )
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, BaseCoreToChip.IoPadInfo( IoPad.BIDIR
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, self.ioPadNames['bidir']
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, 'PAD', ['A', 'Y', 'OE'], [ ( 'SL' , True )
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, ( 'CS' , True )
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, ( 'PU' , False )
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, ( 'PD' , False )
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, ( 'PDRV0', False )
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, ( 'PDRV1', False )
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, ( 'IE' , True )
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] )
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, BaseCoreToChip.IoPadInfo( IoPad.ANALOG
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, self.ioPadNames['analog']
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, 'ASIG5V', ['asig5v'] )
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, BaseCoreToChip.IoPadInfo( IoPad.CORNER
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, self.ioPadNames['corner']
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, None, [] )
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, BaseCoreToChip.IoPadInfo( IoPad.FILLER
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, self.ioPadNames['spacer1']
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, None, [] )
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, BaseCoreToChip.IoPadInfo( IoPad.FILLER
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, self.ioPadNames['spacer5']
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, None, [] )
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, BaseCoreToChip.IoPadInfo( IoPad.FILLER
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, self.ioPadNames['spacer10']
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, None, [] )
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]
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self.cornerCount = 0
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self.spacerCount = 0
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self.padSpacers = []
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self._getPadLib()
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return
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def _getPadLib ( self ):
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"""
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Check that the I/O pad library is present and pre-load the spacer cells.
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"""
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def _cmpPad ( pad ):
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"""Used to sort I/O pads by decreasing width."""
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return pad.getAbutmentBox().getWidth()
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self.padLib = AllianceFramework.get().getLibrary( "iolib" )
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if not self.padLib:
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message = [ 'CoreToChip.libresocio._getPadLib(): Unable to find Alliance "iolib" library' ]
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raise ErrorMessage( 1, message )
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for ioPadInfo in self.ioPadInfos:
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if ioPadInfo.flags & IoPad.FILLER:
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spacerCell = self.padLib.getCell( ioPadInfo.name )
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if spacerCell: self.padSpacers.append( spacerCell )
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else:
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raise ErrorMessage( 1, 'CoreToChip.gf180mcu._getPadLib(): Missing spacer cell "{}"'.format(spacerName) )
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self.padSpacers = sorted( self.padSpacers, key=_cmpPad, reverse=True )
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def getNetType ( self, netName ):
|
||||
if netName.lower().startswith('vss') or netName.lower().startswith('dvss'): return Net.Type.GROUND
|
||||
if netName.lower().startswith('vdd') or netName.lower().startswith('dvdd'): return Net.Type.POWER
|
||||
return Net.Type.LOGICAL
|
||||
|
||||
def isGlobal ( self, netName ):
|
||||
if netName in self.ringNetNames: return True
|
||||
return False
|
||||
|
||||
def getCell ( self, masterCellName ):
|
||||
#cell = self.padLib.getCell( masterCellName )
|
||||
cell = AllianceFramework.get().getCell( masterCellName, Catalog.State.Views )
|
||||
if not cell:
|
||||
raise ErrorMessage( 1, 'libresocio.getCell(): I/O pad library "%s" does not contain cell named "%s"' \
|
||||
% (self.padLib.getName(),masterCellName) )
|
||||
return cell
|
||||
|
||||
def _buildAllGroundPads ( self, ioPadConf ):
|
||||
coreNet = self.core .getNet( ioPadConf.coreSupplyNetName )
|
||||
coronaNet = self.corona.getNet( ioPadConf.coreSupplyNetName )
|
||||
chipNet = self.chip .getNet( ioPadConf.coreSupplyNetName )
|
||||
padNet = self.chip .getNet( ioPadConf.padSupplyNetName )
|
||||
if not coronaNet:
|
||||
coronaNet = Net.create( self.corona, ioPadConf.coreSupplyNetName )
|
||||
coronaNet.setExternal( True )
|
||||
coronaNet.setGlobal ( True )
|
||||
coronaNet.setType ( Net.Type.GROUND )
|
||||
self.icore.getPlug( coreNet ).setNet( coronaNet )
|
||||
if not chipNet:
|
||||
chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName )
|
||||
chipNet.setExternal( True )
|
||||
chipNet.setType ( Net.Type.GROUND )
|
||||
if not padNet:
|
||||
padNet = Net.create( self.chip, ioPadConf.padSupplyNetName )
|
||||
padNet.setExternal( True )
|
||||
padNet.setType ( Net.Type.GROUND )
|
||||
coronaPlug = self.icorona.getPlug( coronaNet )
|
||||
if not coronaPlug.getNet():
|
||||
coronaPlug.setNet( chipNet )
|
||||
self.ringNetNames['DVSS' ] = chipNet
|
||||
#self.ringNetNames['VSS' ] = padNet
|
||||
ioPadConf.pads.append( Instance.create( self.chip
|
||||
, 'p_iovss_{}'.format(ioPadConf.index)
|
||||
, self.getCell(self.ioPadNames['vss']) ) )
|
||||
#self._connect( ioPadConf.pads[0], chipNet, 'VSS' )
|
||||
self._connect( ioPadConf.pads[0], padNet , 'DVSS' )
|
||||
self.groundPadCount += 1
|
||||
self.chipPads += ioPadConf.pads
|
||||
|
||||
def _buildAllPowerPads ( self, ioPadConf ):
|
||||
trace( 550, ',+', '\tgf180mcu.CoreToChip()\n' )
|
||||
trace( 550, '\tcoreSupplyNetName="{}"\n'.format( ioPadConf.coreSupplyNetName ))
|
||||
trace( 550, '\tpadSupplyNetName ="{}"\n'.format( ioPadConf.padSupplyNetName ))
|
||||
coreNet = self.core .getNet( ioPadConf.coreSupplyNetName )
|
||||
coronaNet = self.corona.getNet( ioPadConf.coreSupplyNetName )
|
||||
chipNet = self.chip .getNet( ioPadConf.coreSupplyNetName )
|
||||
padNet = self.chip .getNet( ioPadConf.padSupplyNetName )
|
||||
if not coronaNet:
|
||||
coronaNet = Net.create( self.corona, ioPadConf.coreSupplyNetName )
|
||||
coronaNet.setExternal( True )
|
||||
coronaNet.setGlobal ( True )
|
||||
coronaNet.setType ( Net.Type.POWER )
|
||||
self.icore.getPlug( coreNet ).setNet( coronaNet )
|
||||
if not chipNet:
|
||||
chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName )
|
||||
chipNet.setExternal( True )
|
||||
chipNet.setType ( Net.Type.POWER )
|
||||
self.icorona.getPlug( coronaNet ).setNet( chipNet )
|
||||
trace( 550, '\tchipNet ="{}"\n'.format( chipNet ))
|
||||
if not padNet:
|
||||
padNet = Net.create( self.chip, ioPadConf.padSupplyNetName )
|
||||
padNet.setExternal( True )
|
||||
padNet.setType ( Net.Type.POWER )
|
||||
self.ringNetNames['DVDD'] = chipNet
|
||||
#self.ringNetNames['VDD'] = padNet
|
||||
trace( 550, '\tpadNet ="{}"\n'.format( padNet ))
|
||||
ioPadConf.pads.append( Instance.create( self.chip
|
||||
, 'p_iovdd_{}'.format(ioPadConf.index)
|
||||
, self.getCell(self.ioPadNames['vdd']) ) )
|
||||
#self._connect( ioPadConf.pads[0], chipNet, 'VDD' )
|
||||
self._connect( ioPadConf.pads[0], padNet , 'DVDD' )
|
||||
self.powerPadCount += 1
|
||||
self.chipPads += ioPadConf.pads
|
||||
trace( 550, '-,' )
|
||||
|
||||
def _buildClockPads ( self, ioPadConf ):
|
||||
"""For "GF180MCU" there is no specialized clock I/O pad. So do nothing."""
|
||||
pass
|
||||
|
||||
def _connectClocks ( self ):
|
||||
"""For "GF180MCU" there is no pad internal clock ring. So do nothing."""
|
||||
pass
|
||||
|
||||
def hasCornerCell ( self ):
|
||||
"""Overload of CoreToChip, YES we have dedicated corner cells."""
|
||||
return True
|
||||
|
||||
def hasFillerCells ( self ):
|
||||
"""Overload of CoreToChip, YES we have dedicated filler cells."""
|
||||
return True
|
||||
|
||||
def getCornerCell ( self ):
|
||||
"""Return the model of corner cell."""
|
||||
return self.getCell( self.ioPadNames['corner'] )
|
||||
|
||||
def createSpacer ( self, gapWidth ):
|
||||
"""Return a new instance of spacer cell."""
|
||||
spacerCell = None
|
||||
for candidate in self.padSpacers:
|
||||
if gapWidth >= candidate.getAbutmentBox().getWidth():
|
||||
spacerCell = candidate
|
||||
break
|
||||
if not spacerCell:
|
||||
return None
|
||||
spacer = Instance.create( self.chip
|
||||
, 'pad_spacer_{}'.format( self.spacerCount )
|
||||
, spacerCell )
|
||||
self.spacerCount += 1
|
||||
#self._connect( spacer, self.ringNetNames['vddring'], 'vddring' )
|
||||
self._connect( spacer, self.ringNetNames['DVDD'], 'DVDD' )
|
||||
#self._connect( spacer, self.ringNetNames['gndring'], 'gndring' )
|
||||
self._connect( spacer, self.ringNetNames['DVSS'], 'DVSS' )
|
||||
return spacer
|
||||
|
||||
def createCorner ( self, instanceName=None ):
|
||||
"""Return a new instance of corner cell."""
|
||||
if instanceName is None:
|
||||
instanceName = 'pad_corner_{}'.format( self.cornerCount )
|
||||
corner = Instance.create( self.chip, instanceName, self.getCornerCell() )
|
||||
self.cornerCount += 1
|
||||
self._connect( corner, self.ringNetNames['DVDD'], 'DVDD' )
|
||||
#self._connect( corner, self.ringNetNames['vddcore'], 'vddcore' )
|
||||
self._connect( corner, self.ringNetNames['DVSS'], 'DVSS' )
|
||||
#self._connect( corner, self.ringNetNames['gndcore'], 'gndcore' )
|
||||
return corner
|
||||
Loading…
Reference in New Issue