Fix the support if "iolib" I/O pad.
In CoreToChip, the "iolib" I/O pad library an alternative to the "cmos" one. "cmos" uses the pxlib library while iolib uses a symbolic abstract version of the C4M (real) I/O pad. The initialization is a bit split as the "cmos" library are part of Alliance, while "iolib" is in alliance-check-toolkit. So "iolib" is added at designflow.technos.setupCMOS(). Setup additional configuration parameter directly in: core2chip.niolib.CoreToChip.__init__().
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@ -70,6 +70,8 @@ def setupCMOS ( checkToolkit=None ):
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af = CRL.AllianceFramework.get()
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env = af.getEnvironment()
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env.setCLOCK( '^ck$|m_clock|^clk$' )
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env.addSYSTEM_LIBRARY( library=(Where.checkToolkit / 'cells' / 'niolib').as_posix()
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, mode =CRL.Environment.Append )
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Yosys.setLiberty( Where.cellsTop / 'sxlib' / 'sxlib.lib' )
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ShellEnv.RDS_TECHNO_NAME = (Where.allianceTop / 'etc' / 'cmos.rds').as_posix()
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@ -20,9 +20,11 @@ Core2Chip configuration for the FlexLib I/O pad library ("niolib").
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import sys
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import re
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from ... import Cfg
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from ...Hurricane import DbU, DataBase, UpdateSession, Breakpoint, \
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Transformation , Instance , Net
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from ...CRL import Catalog, AllianceFramework
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from ...CRL import Catalog, AllianceFramework, CellGauge
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from ...helpers import overlay, l, u, n
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from ...helpers.io import ErrorMessage, WarningMessage
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from .core2chip import CoreToChip as BaseCoreToChip, IoNet, IoPad
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@ -40,6 +42,17 @@ class CoreToChip ( BaseCoreToChip ):
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self.ioPadInfos = [ BaseCoreToChip.IoPadInfo( IoPad.BIDIR, 'gpio', 'pad', ['i', 'o', 'oe'] )
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]
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self._getPadLib()
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af = AllianceFramework.get()
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cg = CellGauge.create( 'niolib'
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, 'METAL2' # pin layer name.
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, l( 5.0) # pitch.
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, l(1190.0) # cell slice height.
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, l( 500.0) # cell slice step.
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)
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af.addCellGauge( cg )
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self.conf.chipConf.ioPadGauge = 'niolib'
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self.conf.cfg.chip.padCoreSide = 'North'
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self.conf.cfg.chip.useAbstractPads = True
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return
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def _getPadLib ( self ):
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