Save VHDL model only once in the rsave Cumulus plugin.

* Bug: In cumulus/plugins/rsave.py, the Cells where saveds each time
    one instance of was encountered. Resulting in multiple saves.
    It was, of course, ineficient, but it also triggers a bug
    that seems to happen after multiple save : the VHDL additional
    property was deleted *before* the full hierarchical dump was
    finished.
      Now, we save each Cell only once so it does not occur, but
    should make a deeper investigation later.

crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp

@@ -63,7 +63,7 @@ namespace Vhdl {
         Bit* bit = BitExtension::get( net );
         if (bit) return bit;
 
-        cerr << Error( "PortMap::_lookup() VHDL extension missing on \"%s\"."
+        cerr << Error( "PortMap::_lookup() VHDL extension missing on \"%s\".\n"
                        "        In cell \"%s\"."
                      , getString(net).c_str()
                      , getString(net->getCell()->getName()).c_str()

cumulus/src/plugins/rsave.py

@@ -29,6 +29,9 @@ except Exception as e:
     sys.exit(2)
 
 
+saveds = set()
+
+
 def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0, enableSpice=False ):
     """
     Write back layout to disk if everything has gone fine.
@@ -39,6 +42,12 @@ def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0, enableSpice=False )
     of abutment box for placement, the netlist view must also
     be saved.
     """
+    global saveds
+
+    if depth == 0: saveds.clear()
+    if cell in saveds: return
+    saveds.add( cell )
+    
     framework = CRL.AllianceFramework.get()
     if depth == 0: print( '  o  Recursive Save-Cell.' )
     if cell.isUniquified():             views |= CRL.Catalog.State.Logical