From 1babec2e918dd97a6f14a242916a5f69feb63d2d Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Sat, 21 May 2022 13:02:58 +0200 Subject: [PATCH] Save VHDL model only once in the rsave Cumulus plugin. * Bug: In cumulus/plugins/rsave.py, the Cells where saveds each time one instance of was encountered. Resulting in multiple saves. It was, of course, ineficient, but it also triggers a bug that seems to happen after multiple save : the VHDL additional property was deleted *before* the full hierarchical dump was finished. Now, we save each Cell only once so it does not occur, but should make a deeper investigation later. --- crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp | 2 +- cumulus/src/plugins/rsave.py | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp index d6e37b00..ce3650b5 100644 --- a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp +++ b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp @@ -63,7 +63,7 @@ namespace Vhdl { Bit* bit = BitExtension::get( net ); if (bit) return bit; - cerr << Error( "PortMap::_lookup() VHDL extension missing on \"%s\"." + cerr << Error( "PortMap::_lookup() VHDL extension missing on \"%s\".\n" " In cell \"%s\"." , getString(net).c_str() , getString(net->getCell()->getName()).c_str() diff --git a/cumulus/src/plugins/rsave.py b/cumulus/src/plugins/rsave.py index a4c1b5a2..ac81f9ae 100644 --- a/cumulus/src/plugins/rsave.py +++ b/cumulus/src/plugins/rsave.py @@ -29,6 +29,9 @@ except Exception as e: sys.exit(2) +saveds = set() + + def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0, enableSpice=False ): """ Write back layout to disk if everything has gone fine. @@ -39,6 +42,12 @@ def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0, enableSpice=False ) of abutment box for placement, the netlist view must also be saved. """ + global saveds + + if depth == 0: saveds.clear() + if cell in saveds: return + saveds.add( cell ) + framework = CRL.AllianceFramework.get() if depth == 0: print( ' o Recursive Save-Cell.' ) if cell.isUniquified(): views |= CRL.Catalog.State.Logical