* Change: In cumulus/plugins.chip.powerplane, when the vertical rail is

large enough instead of creating one big via along the horizontal
    cell power lines, we create one big VIA at each end. To avoid to
    create too massive obstructions.
      But the thresold was too high for cmos45, leading to short with
    the clock tree trunk.
This commit is contained in:
Jean-Paul Chaput 2021-10-09 22:51:48 +02:00
parent 5ba4c35d63
commit fd2c92f442
1 changed files with 1 additions and 1 deletions

View File

@ -140,7 +140,7 @@ class HorizontalRail ( Rail ):
, self.axis + self.width//2 )
overlap = stripeBb.getIntersection( chunkBb )
if overlap.isEmpty(): continue
if overlap.getWidth() > 5*viaWidth:
if overlap.getWidth() > 2*viaWidth:
trace( 550, '\t| Large overlap={}\n'.format(overlap) )
via = BigVia( stripe.getNet()
, plane.getLayerDepth(stripe.getLayer())