* Change: In cumulus/plugins.chip.powerplane, when the vertical rail is
large enough instead of creating one big via along the horizontal cell power lines, we create one big VIA at each end. To avoid to create too massive obstructions. But the thresold was too high for cmos45, leading to short with the clock tree trunk.
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@ -140,7 +140,7 @@ class HorizontalRail ( Rail ):
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, self.axis + self.width//2 )
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overlap = stripeBb.getIntersection( chunkBb )
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if overlap.isEmpty(): continue
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if overlap.getWidth() > 5*viaWidth:
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if overlap.getWidth() > 2*viaWidth:
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trace( 550, '\t| Large overlap={}\n'.format(overlap) )
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via = BigVia( stripe.getNet()
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, plane.getLayerDepth(stripe.getLayer())
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