From fd2c92f44290902ee77a60b73a087d5a0803ccd1 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Sat, 9 Oct 2021 22:51:48 +0200 Subject: [PATCH] * Change: In cumulus/plugins.chip.powerplane, when the vertical rail is large enough instead of creating one big via along the horizontal cell power lines, we create one big VIA at each end. To avoid to create too massive obstructions. But the thresold was too high for cmos45, leading to short with the clock tree trunk. --- cumulus/src/plugins/alpha/chip/powerplane.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cumulus/src/plugins/alpha/chip/powerplane.py b/cumulus/src/plugins/alpha/chip/powerplane.py index 19bcf5d0..a7ce2b5b 100644 --- a/cumulus/src/plugins/alpha/chip/powerplane.py +++ b/cumulus/src/plugins/alpha/chip/powerplane.py @@ -140,7 +140,7 @@ class HorizontalRail ( Rail ): , self.axis + self.width//2 ) overlap = stripeBb.getIntersection( chunkBb ) if overlap.isEmpty(): continue - if overlap.getWidth() > 5*viaWidth: + if overlap.getWidth() > 2*viaWidth: trace( 550, '\t| Large overlap={}\n'.format(overlap) ) via = BigVia( stripe.getNet() , plane.getLayerDepth(stripe.getLayer())