Change SkyWater130 Caravel harness connecting strategy.
* Change: In cumulus/plugins/core2chip, instead of the user providing
an explicit mapping towards the harness I/O pins, we expect that
the core block must have I/O pins with names matching thoses of
the harness. That way, connections are automatically made.
* Change: In cumulus/plugins/block/htree, if the root signal of the
H-Tree is a bit from a vector (like "io_in(0)"), then remove the
vector index notation on all the stem name of all the sub-nets.
Done by the unbitify() function: "io_in(0)" => "io_in_bit0".
This commit is contained in:
Jean-Paul Chaput
parent
76d468f6d5
commit
ae1f08f039
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@ -661,7 +661,8 @@ class IoPadConf ( object ):
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reSpecialPads = re.compile( r'^(?P<type>.+)_(?P<index>[\d+])$' )
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m = reSpecialPads.match( self.instanceName )
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else:
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self.flags |= IoPadConf.ALL_POWER
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if self.instanceName is not None:
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self.flags |= IoPadConf.ALL_POWER
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if m:
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self.index = m.group('index')
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if m.group('type') == 'allpower': self.flags |= IoPadConf.ALL_POWER
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@ -771,6 +772,8 @@ class ChipConf ( object ):
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if attr == 'ioPadGauge' and value is not None:
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self.blockConf._loadIoPadGauge( value )
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def ioPadsCount ( self ): return len(self.padInstances)
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def addIoPad ( self, spec, specNb ):
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"""
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Add an I/O pad specification. The spec argument must be of the form:
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@ -15,6 +15,7 @@
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import sys
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import os.path
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import re
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import Cfg
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from Hurricane import Breakpoint, DbU, Box, Transformation, Box, \
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Path, Layer, Occurrence, Net, HyperNet, \
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@ -31,6 +32,16 @@ from plugins.alpha.block.configuration import GaugeConf
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from plugins.alpha.block.spares import Spares
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def unbitify ( rawName ):
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"""
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Remove the bit indexation from the net name, if any.
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"""
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p = re.compile( r'(?P<name>.+)\((?P<index>\d+)\)' )
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m = p.match( rawName )
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if not m: return rawName
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return '{}_bit{}'.format( m.group('name'), m.group('index') )
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# ----------------------------------------------------------------------------
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# Class : "htree.HTree".
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@ -223,7 +234,7 @@ class HTree ( object ):
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buffers of the leafs of the QuadTree.
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"""
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qt = self.spares.quadTree
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qt.bufferTag = self.treeNet.getName()
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qt.bufferTag = unbitify( self.treeNet.getName() )
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qt.runselect()
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qt.rselectBuffer( self.treeIndex
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, self.treeIndex
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@ -239,7 +250,7 @@ class HTree ( object ):
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"""
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bufferConf = self.spares.conf.bufferConf
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quadTree = self.spares.quadTree
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quadTree.bufferTag = self.treeNet.getName()
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quadTree.bufferTag = unbitify( self.treeNet.getName() )
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quadTree.runselect()
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quadTree.rselectBuffer( self.treeIndex, self.treeIndex, self.flags)
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with UpdateSession():
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@ -574,7 +574,7 @@ class ChipConf ( BlockConf ):
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net = self.corona.getNet( masterNet.getName() )
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if not net:
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raise ErrorMessage( 1, 'ChipConf.findPowerAndClockNets(): Missing global net "{}" at corona level.' \
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.format(asterNet.getName()) )
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.format(masterNet.getName()) )
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self._validated = False
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continue
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if netType == Net.Type.GROUND:
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@ -57,7 +57,7 @@ from plugins.checks import oneDriver
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from plugins.alpha.utils import getPlugByName
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from plugins.alpha.block.block import Block
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from plugins.alpha.block.configuration import BlockConf, IoPadConf, ConstantsConf
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# -------------------------------------------------------------------
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# Class : "IoNet".
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@ -155,7 +155,10 @@ class IoNet ( object ):
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@property
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def chipExtNetName ( self ):
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if self._chipExtNetName is not None: return self._chipExtNetName
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if self._flags & IoNet.IsEnable: return 'None'
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if self._flags & IoNet.IsEnable:
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if self.coreToChip.useHarness():
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return 'io_oeb({})'.format( self._index )
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return 'None'
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if self.chipExtNet: return self.chipExtNet.getName()
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s = self._name
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if self._flags & IoNet.IsElem: s += '({})'.format(self._index)
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@ -209,7 +212,7 @@ class IoNet ( object ):
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self.chipExtNet = self.coreToChip.chip.getNet( self.chipExtNetName )
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self.chipIntNet = self.chipExtNet
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if not self.chipExtNet:
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raise ErrorMessage( 1, 'IoNet.buildNets(): Not harness net "{}" to connect core net "{}".' \
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raise ErrorMessage( 1, 'IoNet.buildNets(): No harness net "{}" to connect core net "{}".' \
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.format( self.chipExtNetName, self.coreNet.getName() ))
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# Chip "internal" net, connect Corona instance net to I/O inside the chip.
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if not self.chipIntNet:
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@ -285,7 +288,7 @@ class IoPad ( object ):
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def __str__ ( self ):
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s = '<IoPad "{}" '.format(self.padInstanceName)
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for ioNet in self.nets:
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s += ' {}'.format(ioNet.coreNetName)
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s += ' "{}" <-> "{}"'.format(ioNet.coreNetName,ioNet.chipExtNetName)
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s += ' direction={}'.format(self.direction)
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s += '>'
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return s
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@ -630,33 +633,28 @@ class CoreToChip ( object ):
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def _buildCoreGroundPads ( self, ioPadConf ):
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"""Build I/O pad relateds to core ground signals."""
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if self.useHarness(): return
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raise NotImplementedError( 'coreToChip._buildGroundPads(): This method must be overloaded.' )
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def _buildIoGroundPads ( self, ioPadConf ):
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"""Build I/O pad relateds to pad internal ground signals."""
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if self.useHarness(): return
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raise NotImplementedError( 'coreToChip._buildGroundPads(): This method must be overloaded.' )
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def _buildAllGroundPads ( self, ioPadConf ):
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"""Build I/O pad relateds to ground signals for core and pads."""
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if self.useHarness(): return
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raise NotImplementedError( 'coreToChip._buildGroundPads(): This method must be overloaded.' )
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def _buildCorePowerPads ( self, ioPadConf ):
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"""Build I/O pad relateds to core power signals."""
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if self.useHarness(): return
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raise NotImplementedError( 'coreToChip._buildPowerPads(): This method must be overloaded.' )
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def _buildIoPowerPads ( self, ioPadConf ):
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"""Build I/O pad relateds to pad internal power signals."""
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if self.useHarness(): return
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raise NotImplementedError( 'coreToChip._buildPowerPads(): This method must be overloaded.' )
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def _buildAllPowerPads ( self, ioPadConf ):
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"""Build I/O pad relateds to power signals for core and pads."""
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if self.useHarness(): return
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raise NotImplementedError( 'coreToChip._buildPowerPads(): This method must be overloaded.' )
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raise NotImplementedError( 'coreToChip._buildPowerPads(): This method must be overloaded, on {}' \
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.format(ioPadConf) )
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def _buildClockPads ( self, ioPadConf ):
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"""Build I/O pad relateds to clock signals."""
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@ -665,7 +663,6 @@ class CoreToChip ( object ):
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def _connectClocks ( self ):
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"""Connect inner clocks signal to the corona (towards the core) ."""
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if self.useHarness(): return
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raise NotImplementedError( 'coreToChip._connectClocks(): This method must be overloaded.' )
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def _loadHarness ( self ):
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@ -704,29 +701,37 @@ class CoreToChip ( object ):
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ioPads = []
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clockIoNets = []
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for ioPadConf in self.conf.chipConf.padInstances:
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if self.useHarness():
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ioPadConf.flags = IoPadConf.BIDIR
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trace( 550, ',+', '\tioPadConf={}\n'.format( ioPadConf ))
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if ioPadConf.isAllPower():
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self._buildAllPowerPads( ioPadConf )
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trace( 550, '-' )
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continue
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if ioPadConf.isCorePower():
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self._buildCorePowerPads( ioPadConf )
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trace( 550, '-' )
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continue
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if ioPadConf.isIoPower():
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self._buildIoPowerPads( ioPadConf )
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trace( 550, '-' )
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continue
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if ioPadConf.isAllGround():
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self._buildAllGroundPads( ioPadConf )
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trace( 550, '-' )
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continue
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if ioPadConf.isCoreGround():
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self._buildCoreGroundPads( ioPadConf )
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trace( 550, '-' )
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continue
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if ioPadConf.isIoGround():
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self._buildIoGroundPads( ioPadConf )
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trace( 550, '-' )
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continue
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if ioPadConf.isClock():
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self._buildClockPads( ioPadConf )
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trace( 550, '-' )
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continue
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if self.useHarness():
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ioPadConf.flags = IoPadConf.BIDIR
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ioPadConf.udata = IoPad( self, ioPadConf )
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for netName in ioPadConf.nets:
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if netName is None: continue
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@ -741,12 +746,14 @@ class CoreToChip ( object ):
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else:
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if ioPadConf.isBidir() or ioPadConf.isTristate():
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if coreNet.getName() == ioPadConf.enableNetName:
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trace( 550, '\tFlag core net name "{}" as enable\n'.format( coreNet.getName() ))
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ioNet.setEnable( True )
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if not ioNet.isEnable():
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if not ioNet.isEnable() and not self.conf.useHarness:
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trace( 550, '\tForce pad net name to "{}"\n'.format( ioPadConf.padNetName ))
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ioNet.chipExtNetName = ioPadConf.padNetName
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ioPadConf.udata.addNet( ioNet )
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ioPads.append( ioPadConf )
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trace( 550, '-' )
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trace( 550, '\tProcessed all IoPadConf, looking for orphaned core nets...\n' )
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for coreNet in self.core.getNets():
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if not coreNet.isExternal(): continue
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@ -771,8 +778,6 @@ class CoreToChip ( object ):
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#trace( 550, '\tNon-configured core net {}, adding {}\n'.format(coreNet,directPad) )
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for ioPad in ioPads:
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ioPad.udata.createPad()
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#if self.useHarness():
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# self._connectCorona()
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else:
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self._connectRing()
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self._connectClocks()
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@ -33,6 +33,93 @@ from plugins.alpha.core2chip.core2chip import CoreToChip as BaseCoreToChip, \
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IoNet, IoPad
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# -------------------------------------------------------------------
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# Class : "MatchHarnessIos".
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class MatchHarnessIos ( object ):
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"""
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In case the connections of the core to the I/O pins are not specified
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(empty ioPadsSpecs list), try to guess the connection by names.
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.. note:: Currently, only matching with the (io_in,io_out,io_oeb),
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power and clock are supported.
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"""
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def __init__ ( self, coreToChip ):
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self.coreToChip = coreToChip
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self.digitalIos = []
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for i in range(38):
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self.digitalIos.append( [None, None, None] )
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self.clock = None
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self.digitalVdd = None
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self.digitalVss = None
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@property
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def conf ( self ): return self.coreToChip.conf
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def matchCore ( self ):
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print( ' o Using implicit Caravel harness connections.' )
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reIoIn = re.compile( r'^(?P<name>\w+)\((?P<index>\d+)\)$' )
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for net in self.conf.core.getNets():
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if not net.isExternal(): continue
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if net.isClock():
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self.clock = net
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continue
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if net.isPower():
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self.digitalVdd = net
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continue
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if net.isGround():
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self.digitalVss = net
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continue
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m = reIoIn.match( net.getName() )
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if m:
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index = int( m.group('index') )
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if index >= 38:
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continue
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if m.group('name') == 'io_in':
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self.digitalIos[ index ][0] = net
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elif m.group('name') == 'io_out':
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self.digitalIos[ index ][1] = net
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elif m.group('name') == 'io_oeb':
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self.digitalIos[ index ][2] = net
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else:
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print( WarningMessage('Unable to match "{}" into harness net.'.format( net.getName() )))
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else:
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print( WarningMessage('Unable to match "{}" into harness net.'.format( net.getName() )))
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if self.digitalVdd:
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self.conf.chipConf.addIoPad( (None, None, 'power_0', 'vccd1', self.digitalVdd.getName()), 0 )
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else:
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print( WarningMessage('Missing digital power net in "{}".'.format(self.conf.core.getName())) )
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if self.digitalVss:
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self.conf.chipConf.addIoPad( (None, None, 'ground_0', 'vssd1', self.digitalVss.getName()), 0 )
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else:
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print( WarningMessage('Missing digital ground net in "{}".'.format(self.conf.core.getName())) )
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if self.clock:
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self.conf.chipConf.addIoPad( (None, None, None, 'user_clock2', self.clock.getName()), 0 )
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else:
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print( WarningMessage('Missing digital clock net in "{}".'.format(self.conf.core.getName())) )
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for i in range(38):
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ioNets = self.digitalIos[ i ]
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if ioNets[0] and ioNets[1] and ioNets[2]:
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self.conf.chipConf.addIoPad( ( None, None, None, ioNets[0].getName()
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, ioNets[0].getName()
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, ioNets[1].getName()
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, ioNets[2].getName() ), 0 )
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elif ioNets[0] and not ioNets[1] and not ioNets[2]:
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self.conf.chipConf.addIoPad( ( None, None, None, ioNets[0].getName()
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, ioNets[0].getName() ), 0 )
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elif not ioNets[0] and not ioNets[1] and ioNets[2]:
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self.conf.chipConf.addIoPad( ( None, None, None, ioNets[2].getName()
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, ioNets[2].getName() ), 0 )
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elif not ioNets[0] and not ioNets[1] and not ioNets[2]:
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continue
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else:
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print( WarningMessage( [ 'Incomplete digital connexion to I/O pad "{}".'.format(index)
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, '* In :{}'.format( ioNets[0] )
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, '* Out:{}'.format( ioNets[1] )
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, '* OEb:{}'.format( ioNets[2] ) ]))
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# --------------------------------------------------------------------
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# Class : "sky130.CoreToChip"
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@ -70,6 +157,8 @@ class CoreToChip ( BaseCoreToChip ):
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, 'pad', ['pad', 'padres'] )
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]
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self._getPadLib()
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if self.conf.chipConf.ioPadsCount() == 0:
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MatchHarnessIos( self ).matchCore()
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return
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def _getPadLib ( self ):
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@ -88,80 +177,47 @@ class CoreToChip ( BaseCoreToChip ):
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raise NotImplementedError( 'coreToChip.getCell(): Harness does not provides I/O pad cells.' )
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def _buildCoreGroundPads ( self, ioPadConf ):
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trace( 550, '\tsky130.CoreToChip._buildGroundPowerPads()\n' )
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coreNet = self.core .getNet( ioPadConf.coreSupplyNetName )
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coronaNet = self.corona.getNet( ioPadConf.coreSupplyNetName )
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chipNet = self.chip .getNet( ioPadConf.coreSupplyNetName )
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chipNet = self.chip .getNet( ioPadConf.padSupplyNetName )
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if not coronaNet:
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coronaNet = Net.create( self.corona, ioPadConf.coreSupplyNetName )
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coronaNet.setExternal( True )
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coronaNet.setGlobal ( True )
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coronaNet.setType ( Net.Type.GROUND )
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coronaNet.setExternal ( True )
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coronaNet.setGlobal ( True )
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coronaNet.setDirection( Net.Direction.IN )
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coronaNet.setType ( Net.Type.GROUND )
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self.icore.getPlug( coreNet ).setNet( coronaNet )
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trace( 550, '\tCreated corona ground net: {}\n'.format(coronaNet) )
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if not chipNet:
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chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName )
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chipNet.setExternal( True )
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chipNet.setType ( Net.Type.GROUND )
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raise ErrorMessage( 1, 'Harness do not provide ground net ""{}' \
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.format( ioPadConf.padSupplyNetName ))
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coronaPlug = self.icorona.getPlug( coronaNet )
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if not coronaPlug.getNet():
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coronaPlug.setNet( chipNet )
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self.ringNetNames['vss'] = chipNet
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ioPadConf.pads.append( Instance.create( self.chip
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, 'p_vss_{}'.format(ioPadConf.index)
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, self.getCell(self.ioPadNames['vss']) ) )
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self._connect( ioPadConf.pads[0], chipNet, 'vss' )
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self.groundPadCount += 1
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self.chipPads += ioPadConf.pads
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def _buildIoGroundPads ( self, ioPadConf ):
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padNet = self.chip.getNet( ioPadConf.padSupplyNetName )
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if not padNet:
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padNet = Net.create( self.chip, ioPadConf.padSupplyNetName )
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padNet.setExternal( True )
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padNet.setType ( Net.Type.GROUND )
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self.ringNetNames['iovss'] = padNet
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ioPadConf.pads.append( Instance.create( self.chip
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, 'p_iovss_{}'.format(ioPadConf.index)
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, self.getCell(self.ioPadNames['iovss']) ) )
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self._connect( ioPadConf.pads[0], padNet , 'iovss' )
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self.groundPadCount += 1
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self.chipPads += ioPadConf.pads
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def _buildCorePowerPads ( self, ioPadConf ):
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trace( 550, '\tsky130.CoreToChip._buildCorePowerPads()\n' )
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coreNet = self.core .getNet( ioPadConf.coreSupplyNetName )
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coronaNet = self.corona.getNet( ioPadConf.coreSupplyNetName )
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chipNet = self.chip .getNet( ioPadConf.coreSupplyNetName )
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chipNet = self.chip .getNet( ioPadConf.padSupplyNetName )
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if not coronaNet:
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coronaNet = Net.create( self.corona, ioPadConf.coreSupplyNetName )
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coronaNet.setExternal( True )
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coronaNet.setGlobal ( True )
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coronaNet.setType ( Net.Type.POWER )
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coronaNet.setExternal ( True )
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coronaNet.setGlobal ( True )
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coronaNet.setDirection( Net.Direction.IN )
|
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coronaNet.setType ( Net.Type.POWER )
|
||||
self.icore.getPlug( coreNet ).setNet( coronaNet )
|
||||
trace( 550, '\tCreated corona power net: {}\n'.format(coronaNet) )
|
||||
if not chipNet:
|
||||
chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName )
|
||||
chipNet.setExternal( True )
|
||||
chipNet.setType ( Net.Type.POWER )
|
||||
raise ErrorMessage( 1, 'Harness do not provide power net ""{}' \
|
||||
.format( ioPadConf.padSupplyNetName ))
|
||||
self.icorona.getPlug( coronaNet ).setNet( chipNet )
|
||||
self.ringNetNames['vdd'] = chipNet
|
||||
ioPadConf.pads.append( Instance.create( self.chip
|
||||
, 'p_vdd_{}'.format(ioPadConf.index)
|
||||
, self.getCell(self.ioPadNames['vdd']) ) )
|
||||
self._connect( ioPadConf.pads[0], chipNet, 'vdd' )
|
||||
coronaPlug = self.icorona.getPlug( coronaNet )
|
||||
if not coronaPlug.getNet():
|
||||
coronaPlug.setNet( chipNet )
|
||||
self.powerPadCount += 1
|
||||
self.chipPads += ioPadConf.pads
|
||||
|
||||
def _buildIoPowerPads ( self, ioPadConf ):
|
||||
padNet = self.chip .getNet( ioPadConf.padSupplyNetName )
|
||||
if not padNet:
|
||||
padNet = Net.create( self.chip, ioPadConf.padSupplyNetName )
|
||||
padNet.setExternal( True )
|
||||
padNet.setType ( Net.Type.POWER )
|
||||
self.ringNetNames['iovdd'] = padNet
|
||||
ioPadConf.pads.append( Instance.create( self.chip
|
||||
, 'p_iovdd_{}'.format(ioPadConf.index)
|
||||
, self.getCell(self.ioPadNames['iovdd']) ) )
|
||||
self._connect( ioPadConf.pads[0], padNet , 'iovdd' )
|
||||
self.powerPadCount += 1
|
||||
self.chipPads += ioPadConf.pads
|
||||
|
||||
def _buildClockPads ( self, ioPadConf ):
|
||||
"""For "Sky130" there is no specialized clock I/O pad. So do nothing."""
|
||||
|
|
|
|||
Loading…
Reference in New Issue