Export terminal of I/O pads at chip level.
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3b6b588a74
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@ -17,11 +17,11 @@ from __future__ import print_function
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import sys
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import re
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from operator import itemgetter
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from Hurricane import DbU, Point, Transformation, Interval, Box, \
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Path, Occurrence, UpdateSession, Layer, \
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BasicLayer, Net, Pin, Contact, Segment, \
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Horizontal, Vertical, Diagonal, RoutingPad, \
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Instance, DataBase
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from Hurricane import DbU, Point, Transformation, Interval, Box, \
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Path, Occurrence, UpdateSession, Layer, \
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BasicLayer, Net, Pin, Contact, Segment, Pad, \
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Horizontal, Vertical, Diagonal, RoutingPad, \
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Instance, DataBase, NetExternalComponents
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import CRL
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from CRL import RoutingGauge, RoutingLayerGauge
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import helpers
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@ -329,23 +329,36 @@ class Side ( object ):
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p = None
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if self.conf.ioPadGauge.getName() == 'pxlib':
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p = re.compile( r'p(?P<power>v[sd]{2}[ei])ck_px' )
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if self.conf.ioPadGauge.getName().startswith('phlib'):
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elif self.conf.ioPadGauge.getName().startswith('phlib'):
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p = re.compile( r'p(?P<power>v[sd]{2})ck2_sp' )
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if self.conf.ioPadGauge.getName() == 'niolib':
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elif self.conf.ioPadGauge.getName() == 'niolib':
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p = re.compile( r'(?P<power>(io)?v[sd]{2})' )
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elif self.conf.ioPadGauge.getName() == 'LibreSOCIO':
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p = re.compile( r'IOPad(?P<power>(IO)?V[sd]{2})' )
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if p:
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m = p.match( padInstance.getMasterCell().getName() )
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padName = 'pad'
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if m: padName = m.group( 'power' )
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if m:
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padName = m.group( 'power' )
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if self.conf.ioPadGauge.getName() == 'LibreSOCIO':
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padName = padName.lower()
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padNet = padInstance.getMasterCell().getNet( padName )
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trace( 550, '\tpadName:{} padNet:{}\n'.format(padName,padNet) )
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trace( 550, '\tpadName:{} padNet:{} (power/ground)\n'.format(padName,padNet) )
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if padNet:
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plug = padInstance.getPlug( padNet )
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chipNet = plug.getNet()
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if not chipNet and padNet.isGlobal():
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chipNet = padInstance.getCell().getNet( padNet.getName() )
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if not chipNet:
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if padNet.isGlobal():
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chipNet = padInstance.getCell().getNet( padNet.getName() )
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else:
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print( ErrorMessage( 1, 'Side._placePad(): The "pad" terminal is unconnected on {}.' \
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.format(padInstance.getName()) ))
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if chipNet:
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rp = RoutingPad.create( chipNet, Occurrence(plug), RoutingPad.BiggestArea )
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rp = RoutingPad.create( chipNet, Occurrence(plug), RoutingPad.BiggestArea )
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pad = Pad.create( chipNet
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, rp.getOccurrence().getEntity().getLayer()
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, rp.getBoundingBox() )
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NetExternalComponents.setExternal( pad )
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return
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def _placePads ( self ):
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