zero level outputs when the user project area is powered down.
That allows the synthesis tools to buffer these outputs. The
protection from floating inputs is left as-is, but all logic that
was unnecessary to be specified by gate instances has been changed
to RTL. This leaves only a handful of signals (logic analyzer input,
user IRQ, and wishbone data out and acknowledge out) to be handled
by explicit logic gate instances.
~ fix typo in referencing variables in sdc file
~ fine tune parameters to get the design to route
with cts and diode insertion
!important:
depends on SAVE_LIB patch from openlane
the left hand side of caravan from gpio_defaults_block_14 to
gpio_defaults_block_25. Otherwise, the script that generates the
custom user configuration won't be able to change the defaults
for GPIO 25.
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition
- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
- to add obstruction before pdn
- to manually insert buffers on some ports
- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn
- misc changes:
* fix openlane makefile to properly detect interactive script
!important still need to run dynamic simulations
!important depends on some updates to openlane
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`
!IMPORTANT - still need to run dynamic simulations
tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice.
The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker)
will pass the consistency check.
Co-authored-by: Risto Bell <rb@efabless.com>
from the data and replace them with a single flop clocked on the
negative edge of the serial clock. This will completely avoid hold
violations by ensuring that the block's output data bit does not
change anywhere near the clock rising edge, so clocks do not have
to be tightly aligned among all of the GPIO blocks.
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
xschem-generated schematic netlist.
NOTE: None of these modifications change the function of any circuit. The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled. It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.
* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).
* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
* Modified the set_user_id.py script so that mode "-report" returns
a valid value, instead of throwing an error, because the "info.yaml"
file was removed without due consideration of the side effects.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
it will recognize all block cell types in the gate level netlist
after having been run previously. The former code was only looking
for numeric digits in the cell name, but the cell name suffix is
hex, not integer, and so the script needs to add a check for the
letters A-F or a-f in the cell name suffix. This is not an
immediate issue because the two default values used are "0403" and
"1803" and happen not to have any alphabetic hex digits. But if
it were deemed necessary to change a default, then this script
should not break.
does not pass through an inverter, so that the input can remain
unconnected. Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state. This is a simple logic refactoring
and does not change the logic function. The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
* Corrects four signals which were missing from the caravan top level
(management output and output enable to GPIO 0 and 1---these errors
would have prevented the houskeeping SPI from working on caravel).
Corrected RTL verilog (source of the error), GL verilog, and layout.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Create lvs-cvc.rst
* user_project_analog_wrapper -> user_analog_project_wrapper
* Added table
* Update lvs-cvc.rst
* Create lvs_cvc_mpw4.rst
Initial steps for LVS and CVC-RV for MPW-4 slot-002
* Update lvs_cvc_mpw4.rst
diode and short errors
* daily progress
`simple_por` changes to `caravel.v`
* Update lvs_cvc_mpw4.rst
* Changed int (truncate) to round to correct gpio_default error.
* Replace gpio_defaults_block for gpio 0-4 correctly.
Remove old versions of gpio_defaults_block 0403 and 1803.
* Removed local CVC-RV docs not ready for commit.
* Quick fix to a route that was hand-corrected from an Openlane
short but which is just shy of the minimum width for metal4.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Fixes an error in the gen_gpio_defaults.py script that is incompatible
with the use of indexed arrays for five of the gpio_defaults_block
instances. Previously this was handled by manually changing the names
in the layout file. This script avoids the need for manual modification
by directly handling the indexed notation. Also, this extends the
modifications made to the layout to include the first five defaults
blocks; otherwise, the first five defaults blocks are not changed and
the defaults will be wrong for the housekeeping SPI pins.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Mohamed Shalan
M0stafaRady
M0stafaRady
RTimothyEdwards
Tim Edwards
Marwan Abbas
PriyankaDilip
kareem
Kareem Farid
sto6
Jeff DiCorpo
matt venn
Anton Blanchard
Mitch Bailey
Ian Zhang