Commit Graph

70 Commits

Author SHA1 Message Date
Tim Edwards d5ef31e391 Added an empty management core wrapper to the caravel top level. 2021-11-12 12:17:52 -05:00
manarabdelaty 856539ca59 Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
Tim Edwards 112ed53751 Modified the Makefile so that "make lvs-gds-" works better (maybe
not perfectly) when run on chip-io or anything with a pad cell.
2021-11-11 08:48:14 -05:00
Tim Edwards 27fdba364b Added user 1.8V power supply rails to the chip_io and chip_io_alt
layouts.  Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell.  These
internal lines were previously in the power routing cells.
2021-11-10 17:13:43 -05:00
Tim Edwards 7820f7a969 Updated the floorplan. 2021-11-10 12:21:22 -05:00
Tim Edwards 38dbd8d5d9 Added logo graphic for Caravan. 2021-11-09 22:47:31 -05:00
Tim Edwards 8da7d5124b Added a logo for Caravel. 2021-11-09 17:18:20 -05:00
manarabdelaty 89bb33fbc0 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-08 13:35:16 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
Tim Edwards 4a27ea4c6b Finished first draft of the gen_gpio_defaults.py script, which now
makes backup copies of caravel and caravan layouts and replaces the
cell name of any gpio defaults block that is changed from the
contents of user_defines.v.  NOTE:  user_defines.v ultimately must
reside in the user project.  The Makefile should copy the user's
version into the caravel directory space before running the script,
or else the script should be rewritten to reference the user's
project area when reading user_defines.v.
2021-11-07 21:51:00 -05:00
Tim Edwards 27e0c94997 Added caravan top level and seeded with the GPIO control blocks,
default blocks, and updated copyright.
2021-11-06 22:34:49 -04:00
Tim Edwards cd906cbf8a Updated the copyright block for the new designs. Added caravel
layout and placed the GPIO control blocks and default blocks.
2021-11-06 22:13:19 -04:00
Tim Edwards 6a93ea582d Added a script which parses the file "user_defines.v" in
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file.  Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
2021-11-06 21:19:42 -04:00
Tim Edwards f53590d4b5 Split the layout of the GPIO defaults block into three versions, for the
three parameterized values used in the RTL verilog.  Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
2021-11-06 13:28:26 -04:00
Tim Edwards 33140b67a5 Edited the gpio_defaults_block layout like the user_id_programming
cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
2021-11-06 12:59:49 -04:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency 2021-11-05 18:36:43 +02:00
manarabdelaty e68664101c Update gpio_control_block 2021-11-05 16:54:55 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00
manarabdelaty 8b055a380c Add top level makefile 2021-11-04 16:16:39 +02:00
Tim Edwards b8dda9c3b1 (1) Corrected an error from a recent commit where the reset was
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping.  (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins.  The load pin propagates through the chaing like the
other two.  Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
2021-11-03 23:18:36 -04:00
Tim Edwards ba932643e6 Changed the chip_io and chip_io_alt layouts to implement the
continuous ring of vccd and vssd.  The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
2021-11-03 15:57:46 -04:00
Tim Edwards e09640425a Added the user-power-down version of hkspi (hkspi_power) to the list
of patterns to run in the Makefile for verilog dv, since that pattern
has been debugged and now runs correctly.
2021-11-03 11:33:13 -04:00
Tim Edwards 3b89cf0efa Corrected the clock signal into the housekeeping module, which was
incorrectly assigned to the clock on the user side of the managment
protect block, causing it to be undefined when the user area power
supply is down.  The "hkspi_power" testbench which tests using the
housekeeping SPI while the user area power is grounded now works
correctly.
2021-11-03 11:30:39 -04:00
Tim Edwards fe1fcbc3a5 Modified the padframe definition to keep the vccd domain continuous
around the entire padframe.  The vccd1 and vccd2 domains are local
to their respective pads, and any bus routing must be done inside
the padframe.  This means that all pads operate on global vddio for
3.3V as before, but also global vccd for 1.8V.  The user 1.8V voltage
domain only goes as far as the input to the GPIO control block.
2021-11-03 10:53:09 -04:00
Tim Edwards 1d359690ac Added testbench for checking that the housekeeping SPI is accessible when
the user area is powered down.  Because this requires some changes to the
padframe definition, this testbench currently fails.
2021-11-02 21:58:47 -04:00
Tim Edwards 9fb3925649 Updated the OSHW (open source hardware) icon graphic layout, which was
badly digitized, and not taking advantage of the allowance of 45 degree
angles on metal5.
2021-11-01 17:25:34 -04:00
Tim Edwards dd66d1e5ca Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 21:43:09 -04:00
Tim Edwards a2aacdb5d2 Removed some commented-out test code from sram_exec.c to make the
code clearer and less cluttered.
2021-10-31 17:06:05 -04:00
Tim Edwards a360b77618 Added a testbench that demonstrates copying a portion of a program in
flash into SRAM and executing it.
2021-10-31 16:58:44 -04:00
Tim Edwards 11fe006532 Added documentation on the clocking and DLL blocks. 2021-10-29 12:09:20 -04:00
Tim Edwards 1397ceb464 Added simple floorplan drawings for caravel. 2021-10-28 22:49:59 -04:00
Tim Edwards 00e0a5f603 Corrected the two failing testbenches (which needed fixing because
the implementation of the housekeeping module changed the addresses
of the signals being exercised).
2021-10-28 22:20:46 -04:00
Tim Edwards 787f1c3dae Added back wishbone verification tests, specifically those related
to areas not part of the management SoC, including chip_io,
mgmt_protect, and mprj_ctrl and sysctrl_wb (which are now part of
housekeeping).  The two housekeeping tests fail and need to be
debugged.
2021-10-28 17:26:06 -04:00
Tim Edwards 11165bfe3d Added entries in defs.h for the new input enable lines from the
management SoC to the management protect block, and updated the
documentation to include the new wishbone interface for those
signals, and the additional signals on the management SoC pinout.
2021-10-28 10:13:14 -04:00
Tim Edwards 3a57940371 Revised the management protect block to include protections against
an unconnected wishbone bus (unconnected inputs).  Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
2021-10-27 19:36:43 -04:00
Tim Edwards a67cbcb01c Added back a couple more files related to the user ID programming block. 2021-10-26 10:40:55 -04:00
Tim Edwards a7148378a0 Added as many of the magic database layout files as are expected to remain
unchanged between the caravel and caravel_openframe repositories.
2021-10-26 10:27:03 -04:00
Tim Edwards 1e7400c0ac Removed unused definitions from user_defines.v, and added more
explanatory comments.
2021-10-25 16:36:18 -04:00
Tim Edwards 745eee1baa Created an "open frame" version of caravan (and revised the one for
caravel, since it had not been updated since a number of changes to
the caravel top level module).
2021-10-25 16:29:12 -04:00
Tim Edwards bc9944ce20 Updated the caravan netlist and implemented the caravan testbench. 2021-10-25 15:08:13 -04:00
Tim Edwards a7fec91c4c Update to the back-door wishbone access to housekeeping to better
implement the arbitration between SPI and back-door.  The back-door
access flags when it is going to do a read or write, and the SPI
can have an invalid read or fail a write if the SPI is too fast,
but the wishbone access should be valid.  As long as the SPI is
much slower than the core clock (say, 1MHz) then there should be no
contention, which means that contention can always be avoided simply
by slowing the SPI signaling down.
2021-10-24 16:58:47 -04:00
Tim Edwards e6a94449ce Modified the housekeeping SPI to generate a read strobe (or rather
status) so that between rdstb and wrstb, the SPI signals when it is
about to read or write a byte.  The back-door wishbone interface then
stalls the CPU during these periods.  That allows the CPU to continue
running while the SPI is being accessed without data collisions and
without having to stall for the entire time CSB is held low.
Because SCK is asynchronous to the clock, rare collisions are still
possible;  this is not expected to be an issue but might be worth
investigating.
2021-10-23 22:06:24 -04:00
Tim Edwards e5c90daddd Implemented a system for setting the GPIO power-on defaults through
via programming.  The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file.  For the verilog, they are
applied as parameters.  For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
2021-10-23 17:18:30 -04:00
Tim Edwards a8ccbf2890 Added block diagrams for documentation. 2021-10-22 12:01:08 -04:00
Tim Edwards 3ffe67e652 Changed the SRAM read-only port signal names to match the change
made to the management SoC wrapper definition---this is just
making the nomenclature better (no functional change).
2021-10-22 11:51:07 -04:00
Tim Edwards a15593b217 Added a simple block diagram of the organization of the Caravel
harness chip.
2021-10-21 22:40:46 -04:00
Tim Edwards e474dbbc99 Corrected the last testbenches, added a new testbench for the spi_master
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master.  Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
2021-10-21 19:48:24 -04:00