Tim Edwards
bd4f053ec1
Updated I/O layouts with constant_block instances from M. Hosni's
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fork of caravel (layout .mag file not copied into this commit).
The layouts of both chip_io and chip_io_alt are believed to be
complete, but need verification (with LVS).
2022-10-08 16:48:59 -04:00
mo-hosni
da9e607760
added constant_block gds
2022-10-08 12:13:09 -07:00
mo-hosni
dde6e034e0
added constant_block view
2022-10-08 12:05:53 -07:00
Tim Edwards
fd29bb3442
Generated new chip_io_alt layout to match the chip_io changes in
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the previous commit. Fixed a few minor errors in the chip_io
layout. Waiting on layout of constant_block to finish.
2022-10-08 14:05:46 -04:00
RTimothyEdwards
c0d6011ee8
Apply automatic changes to Manifest and README.rst
2022-10-08 16:07:53 +00:00
Tim Edwards
d1a3922dbb
Initial commit for rework of chip_io and chip_io_alt layouts;
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includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
2022-10-08 12:05:10 -04:00
M0stafaRady
7b2994e70e
Apply automatic changes to Manifest and README.rst
2022-10-08 13:26:20 +00:00
M0stafaRady
e94a8e0477
add test la test
2022-10-08 06:25:26 -07:00
M0stafaRady
d90001eac2
update caravel.py to disable bin 3 also
2022-10-08 01:56:41 -07:00
mo-hosni
b88648bbae
compress gds
2022-10-07 17:03:21 -07:00
mo-hosni
d6ca7f9091
rehardened housekeeping after rtl update, and fixed all hold and transition violations.
2022-10-07 16:59:01 -07:00
Mohamed Hosni
5c38e38767
Merge branch 'efabless:caravel_redesign' into caravel_redesign
2022-10-07 16:52:16 -07:00
R. Timothy Edwards
7b271a7808
Effectively reverted the change to add spare logic blocks near each ( #157 )
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* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-10-07 09:28:13 -07:00
M0stafaRady
2dc29bb207
comment disabling the housekeeping at the begining of each test as it's not needed anymore
2022-10-07 07:02:58 -07:00
M0stafaRady
0f167fc041
update timeout for gpio_all_i_pd and gpio_all_i_pu
2022-10-07 07:02:09 -07:00
M0stafaRady
fcb21cc0f7
Merge branch 'cocotb' of github.com:efabless/caravel into cocotb
2022-10-07 06:42:15 -07:00
M0stafaRady
f072e9cb2d
Add gpio_all_i_pd
2022-10-07 06:41:21 -07:00
M0stafaRady
0aa649265e
Apply automatic changes to Manifest and README.rst
2022-10-07 13:07:22 +00:00
M0stafaRady
6f832589c0
merge caravel_redesign
2022-10-07 06:06:14 -07:00
M0stafaRady
e1eba1d534
update gpio_all_i_pu test
2022-10-07 06:04:18 -07:00
kareem
6d1d618974
reharden!: gpio_control_block
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- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations
!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
2022-10-07 05:02:14 -07:00
Jeff DiCorpo
0e3badac29
152 add pass thru for clock and reset ( #154 )
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* update caravel.v and caravan.v for clock and reset passthru.
* Apply automatic changes to Manifest and README.rst
* Apply automatic changes to Manifest and README.rst
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu>
Co-authored-by: shalan <shalan@users.noreply.github.com>
2022-10-07 01:36:26 -07:00
jeffdi
12358ee251
Apply automatic changes to Manifest and README.rst
2022-10-07 08:25:07 +00:00
R. Timothy Edwards
cfbe353290
Added spare logic blocks for GPIO ( #153 )
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* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 01:24:01 -07:00
R. Timothy Edwards
be25ae7476
Remove SRAM read-only interface ( #151 )
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* Removed the SRAM read-only interface by wrapping all related code
in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 01:23:07 -07:00
RTimothyEdwards
318e836af5
Apply automatic changes to Manifest and README.rst
2022-10-06 19:59:16 +00:00
Tim Edwards
a07d0d5dac
Fixed one small error in the housekeeping module that was surfaced
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by the pull-up/pull-down testbench.
2022-10-06 15:57:45 -04:00
M0stafaRady
3eb0b11380
update verify_cocotb.py to remove vcs generate files
2022-10-06 11:18:48 -07:00
M0stafaRady
4f483adb36
update hk_regs_wr_wb_cpu test to include all house keeping regs
2022-10-06 11:16:07 -07:00
M0stafaRady
7e407e1155
Add test hk_disable
2022-10-06 10:12:12 -07:00
M0stafaRady
28b453783f
Add clock redirect test
2022-10-06 09:20:06 -07:00
R. Timothy Edwards
0d6c3f9519
Merge pull request #135 from efabless/make_CSB_a_pullup
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Change CSB pin (GPIO 3) to be a weak pull-up input
2022-10-06 11:41:15 -04:00
RTimothyEdwards
b140fdb6ac
Apply automatic changes to Manifest and README.rst
2022-10-06 15:40:23 +00:00
R. Timothy Edwards
611c320eed
Merge branch 'caravel_redesign' into make_CSB_a_pullup
2022-10-06 11:39:22 -04:00
R. Timothy Edwards
45692fea7e
Merge pull request #122 from efabless/fix_direct_power_connections
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Fix direct power connections
2022-10-06 11:33:41 -04:00
M0stafaRady
fb34d9a541
update input tests to cover the gpio from 32 to 37
2022-10-06 05:32:46 -07:00
M0stafaRady
a69185dfca
update verify_cocotb.py script to collect coverage only when -cov is passed
2022-10-06 04:44:55 -07:00
M0stafaRady
1bc78c4eea
update verify_cocotb.py script to collect coverage only when -cov is passed
2022-10-06 04:43:02 -07:00
M0stafaRady
8e72d5e13e
Add test uart_loopback
2022-10-06 03:12:44 -07:00
M0stafaRady
6830c79ae8
fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX);
2022-10-06 02:14:59 -07:00
Tim Edwards
42805f767e
Removed some references to mgmt_soc_litex files that had been added
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to caravel_netlists.v when attempting to determine if the
verification testbenches could be run from caravel referencing
caravel_mgmt_soc_litex instead of the other way around. This file
has been reverted back to its original form.
2022-10-05 21:43:29 -04:00
RTimothyEdwards
77b47e3b5c
Apply automatic changes to Manifest and README.rst
2022-10-06 01:39:57 +00:00
Tim Edwards
e2556cc11b
Removed the SPARE_LOGIC_BLOCK ifdef...endif from around the spare
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logic in caravel.v and caravan.v. These had been added to the
caravel_stanford branch because the spare logic blocks are not
usefully synthesizable.
2022-10-05 21:37:55 -04:00
RTimothyEdwards
6831b85e3c
Apply automatic changes to Manifest and README.rst
2022-10-06 01:34:14 +00:00
R. Timothy Edwards
268f5dd7e9
Merge branch 'caravel_redesign' into fix_direct_power_connections
2022-10-05 21:33:17 -04:00
Tim Edwards
76627f546b
Reverting the Makefile, which somehow got picked up from the wrong
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branch and committed into this one.
2022-10-05 21:31:25 -04:00
RTimothyEdwards
73c0d2b805
Apply automatic changes to Manifest and README.rst
2022-10-06 01:07:43 +00:00
Tim Edwards
83f58cbe65
Added back a "genvar" statement that was deleted from housekeeping
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along with an unused block, but was needed elsewhere.
2022-10-05 21:05:58 -04:00
RTimothyEdwards
eaa21ea87b
Apply automatic changes to Manifest and README.rst
2022-10-06 00:55:06 +00:00
Tim Edwards
72341326e2
Corrected a typo in the definition of the mgmt_io_oeb vector in
...
caravel.v, which should be the same as mgmt_io_in and mgmt_io_out
and should equal the number of user I/O pads (38).
2022-10-05 20:52:21 -04:00