gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
* Removed the SRAM read-only interface by wrapping all related code
in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
the left hand side of caravan from gpio_defaults_block_14 to
gpio_defaults_block_25. Otherwise, the script that generates the
custom user configuration won't be able to change the defaults
for GPIO 25.
Corrected the pad constant connections to all be in the correct domain
(1.8V or 3.3V). Created a new "constant_block" module that generates
a single constant 1 and 0 value in the 1.8V domain, and used 7 of these
in the chip_io (and chip_io_alt) modules to create the 1.8V domain
constant signals for the seven pads belonging to the management (clock,
reset, flash SPI, and management GPIO).
inputs that are permanently tied low or high come from either
the local "TIE" pad connections (if they are in the 3.3V
domain) or from a constant one wire in the 1.8V domain that
is generated in the gpio_control_block module and exported
to the chip_io (or chip_io_alt) module.
* Corrects four signals which were missing from the caravan top level
(management output and output enable to GPIO 0 and 1---these errors
would have prevented the houskeeping SPI from working on caravel).
Corrected RTL verilog (source of the error), GL verilog, and layout.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* (1) Modified the .magicrc file to set a default for PDK if not set in the
environment. (2) Fixed the user ID programming layout to not leave holes
behind when the script moves the vias around (similar to the handling of
the GPIO defaults block). (3) Added substrate isolation to gpio_control_block
and fixed the path references to the standard cells. (4) Fixed the four
missing routes on the Caravan top level. (5) Reinstated the large rendered
labels for the pads on both caravel and caravan. (6) Corrected the top
level gate-level netlist for caravan to add the missing pins to the
management core wrapper. (7) Did the same for the caravan top level RTL.
(8) Created scripts to run full LVS including extracting the management
core wrapper and reading all gate-level verilog submodules. (9) Moved all
of the LVS scripts to the scripts directory.
* Apply automatic changes to Manifest and README.rst
* Made the changes from pull request #73 as they did not get merged
successfully, and if merged now they will generate conflicts with
this pull request in scripts/set_user_id.py. So it's easier to
just manually add them to this pull request.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one
* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it
* Apply automatic changes to Manifest and README.rst
* add caravan power routing lef
* - update mag and def view of caravan
- add_macro_placement for fake cell
* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines. Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag. It may be
worth cherry-picking the files to merge and exclude those layouts.
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
* Corrected the issue reported on the github issue tracker (#34)
in which the use of "clocking" as an instance name in caravel and
caravan conflicts with the system verilog keyword of the same
name.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be). This is
functionally the same. Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good). Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change. This
was the only change affecting layout. Also: Revised the "pll"
testbench. This is still ongoing work. Also: Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre. Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core. Also: Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
problems that had been fixed recently in caravel, and which cause
the caravan testbench to break, but which were not noticed; (2)
corrected the count of gpio_control_block modules, which was one
off, with two of them overlapping (not sure how that even passes
simulation, but it did); (3) fixed a power connection in the
caravel chip_io, which should have caused chip_io to fail LVS,
so apparently LVS was not run on chip_io. . .
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
(clock -> clock_core in caravel_clocking, VPWR -> vccd_core and
VGND -> vssd_core in the instances of modules that were pulled from
the management SoC to the top level).
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping. (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins. The load pin propagates through the chaing like the
other two. Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
incorrectly assigned to the clock on the user side of the managment
protect block, causing it to be undefined when the user area power
supply is down. The "hkspi_power" testbench which tests using the
housekeeping SPI while the user area power is grounded now works
correctly.
an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
Tim Edwards
Jeff DiCorpo
jeffdi