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caravel
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Added a new module with "spare logic" for metal mask fixes.

This commit is contained in:
Tim Edwards 2021-11-24 09:23:22 -05:00
parent 9b1a18a15e
commit 2b156997cb
5 changed files with 187 additions and 21 deletions
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23
verilog/rtl/caravan.v
View File

@ -1371,5 +1371,28 @@ module caravan (
.X(rstb_l)
);
// Spare logic for metal mask fixes
wire [15:0] spare_xi_nc;
wire [3:0] spare_xib_nc;
wire [7:0] spare_xna_nc;
wire [7:0] spare_xno_nc;
wire [7:0] spare_xmx_nc;
wire [7:0] spare_xfq_nc;
wire [7:0] spare_xfqn_nc;
spare_logic_block spare_logic [3:0] (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),
`endif
.spare_xi(spare_xi_nc),
.spare_xib(spare_xib_nc),
.spare_xna(spare_xna_nc),
.spare_xno(spare_xno_nc),
.spare_xmx(spare_xmx_nc),
.spare_xfq(spare_xfq_nc),
.spare_xfqn(spare_xfqn_nc)
);
endmodule
// `default_nettype wire

3
verilog/rtl/caravan_netlists.v
View File

@ -63,6 +63,8 @@
`include "gl/gpio_defaults_block.v"
`include "gl/gpio_logic_high.v"
`include "gl/xres_buf.v"
`include "gl/spare_logic_block.v"
`include "gl/mgmt_core_wrapper.v"
`include "gl/caravan.v"
`else
`include "digital_pll.v"
@ -81,6 +83,7 @@
`include "gpio_defaults_block.v"
`include "gpio_logic_high.v"
`include "xres_buf.v"
`include "spare_logic_block.v"
`include "mgmt_core_wrapper.v"
`include "caravan.v"
`endif

23
verilog/rtl/caravel.v
View File

@ -1426,5 +1426,28 @@ module caravel (
.X(rstb_l)
);
// Spare logic for metal mask fixes
wire [15:0] spare_xi_nc;
wire [3:0] spare_xib_nc;
wire [7:0] spare_xna_nc;
wire [7:0] spare_xno_nc;
wire [7:0] spare_xmx_nc;
wire [7:0] spare_xfq_nc;
wire [7:0] spare_xfqn_nc;
spare_logic_block spare_logic [3:0] (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),
`endif
.spare_xi(spare_xi_nc),
.spare_xib(spare_xib_nc),
.spare_xna(spare_xna_nc),
.spare_xno(spare_xno_nc),
.spare_xmx(spare_xmx_nc),
.spare_xfq(spare_xfq_nc),
.spare_xfqn(spare_xfqn_nc)
);
endmodule
// `default_nettype wire

3
verilog/rtl/caravel_netlists.v
View File

@ -61,6 +61,8 @@
`include "gl/gpio_defaults_block.v"
`include "gl/gpio_logic_high.v"
`include "gl/xres_buf.v"
`include "gl/spare_logic_block.v"
`include "gl/mgmt_core_wrapper.v"
`include "gl/caravel.v"
`else
`include "digital_pll.v"
@ -79,6 +81,7 @@
`include "gpio_defaults_block.v"
`include "gpio_logic_high.v"
`include "xres_buf.v"
`include "spare_logic_block.v"
`include "mgmt_core_wrapper.v"
`include "caravel.v"
`endif

156
verilog/rtl/spare_logic_block.v
View File

@ -1,43 +1,157 @@
module spare_logic_block (
`ifdef USE_POWER_PINS
inout vccd,
inout vssd,
`endif
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
output wire spare_x1
`default_nettype none
// Spare logic block. This block can be used for metal mask fixes to
// a design. It is much larger and more comprehensive than the simple
// "macro_sparecell" in the HD library, and contains flops, taps, muxes,
// and diodes in addition to the inverters, NOR, NAND, and constant
// gates provided by macro_sparecell.
module spare_logic_block (
`ifdef USE_POWER_PINS
inout vccd,
inout vssd,
`endif
output [3:0] spare_xi, // Inverter outputs
output spare_xib, // Big inverter output
output [1:0] spare_xna, // NAND outputs
output [1:0] spare_xno, // NOR outputs
output [1:0] spare_xmx, // Mux outputs
output [1:0] spare_xfq, // Flop noninverted output
output [1:0] spare_xfqn // Flop inverted output
);
sky130_fd_sc_hd__conb_1 spare_logic_high (
`ifdef USE_POWER_PINS
wire [3:0] spare_logic_nc;
wire [3:0] spare_xi;
wire spare_xib;
wire [1:0] spare_xna;
wire [1:0] spare_xno;
wire [1:0] spare_xmx;
wire [1:0] spare_xfq;
wire [1:0] spare_xfqn;
wire [26:0] spare_logic1;
wire [26:0] spare_logic0;
sky130_fd_sc_hd__conb_1 spare_logic_const [26:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.HI(spare_logic1_0),
.LO(spare_logic0_0)
`endif
.HI(spare_logic1),
.LO(spare_logic0)
);
sky130_fd_sc_hd__conb_1 spare_logic_high (
`ifdef USE_POWER_PINS
sky130_fd_sc_hd__inv_2 spare_logic_inv [3:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.HI(spare_logic1_1),
.LO(spare_logic0_1)
`endif
.Y(spare_xi),
.A(spare_logic0[3:0])
);
sky130_fd_sc_hd__inv_2 spare_logic_inv_0 (
`ifdef USE_POWER_PINS
sky130_fd_sc_hd__inv_8 spare_logic_biginv (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.X(spare_x1),
.A(spare_logic0_1)
`endif
.Y(spare_xib),
.A(spare_logic0[4])
);
sky130_fd_sc_hd__nand2_2 spare_logic_nand [1:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Y(spare_xna),
.A(spare_logic0[6:5]),
.B(spare_logic0[8:7])
);
sky130_fd_sc_hd__nor2_2 spare_logic_nor [1:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Y(spare_xno),
.A(spare_logic0[10:9]),
.B(spare_logic0[12:11])
);
sky130_fd_sc_hd__mux2_2 spare_logic_mux [1:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.X(spare_xmx),
.A0(spare_logic0[14:13]),
.A1(spare_logic0[16:15]),
.S(spare_logic0[18:17])
);
sky130_fd_sc_hd__dfbbp_1 spare_logic_flop [1:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.Q(spare_xfq),
.Q_N(spare_xfqn),
.D(spare_logic0[20:19]),
.CLK(spare_logic0[22:21]),
.SET_B(spare_logic0[24:23]),
.RESET_B(spare_logic0[26:25])
);
sky130_fd_sc_hd__tapvpwrvgnd_1 spare_logic_tap [1:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd)
`endif
);
sky130_fd_sc_hd__diode_2 spare_logic_diode [3:0] (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
`endif
.DIODE(spare_logic_nc)
);
endmodule
`default_nettype wire