17 Commits

Author	SHA1	Message	Date
M0stafaRady	745b3e3e2c	cocotb - skip write and read from xfer ... because the write reg is diffrent than the read one	2022-10-25 08:00:51 -07:00
M0stafaRady	425b59249d	cocotb - Fix timeout of all tests	2022-10-24 04:59:04 -07:00
M0stafaRady	d13743ae41	cocotb - Add spi_rd_wr_nbyte test	2022-10-18 11:43:40 -07:00
M0stafaRady	ceac6defa1	fix some tests for gatelevel	2022-10-13 04:05:12 -07:00
M0stafaRady	e8870d6a8b	fix errors for gate level	2022-10-12 10:29:56 -07:00
M0stafaRady	2a5c7b876b	fix some timeout and errors due to cpu became slower and sram interface are deleted	2022-10-11 14:00:49 -07:00
M0stafaRady	688429eeda	move caravel.py, cpu.py ... to interfaces directory	2022-10-10 04:50:45 -07:00
M0stafaRady	4f483adb36	update hk_regs_wr_wb_cpu test to include all house keeping regs	2022-10-06 11:16:07 -07:00
M0stafaRady	7e407e1155	Add test hk_disable	2022-10-06 10:12:12 -07:00
M0stafaRady	28b453783f	Add clock redirect test	2022-10-06 09:20:06 -07:00
M0stafaRady	8e21a2f722	Add test pll	2022-10-05 13:58:36 -07:00
M0stafaRady	e2b345dcbb	Add new test user_pass_thru_rd	2022-10-04 10:55:53 -07:00
M0stafaRady	11330823b7	Add hk_regs_wr_wb_cpu test	2022-10-04 03:24:15 -07:00
M0stafaRady	cb929cb329	Fix housekeeping spi tests	2022-10-02 05:37:27 -07:00
M0stafaRady	53e868abdf	add clock to the output od configuration function	2022-10-01 12:34:53 -07:00
M0stafaRady	555488c832	fix timeout values to the passing number of cycles required + 10%	2022-10-01 04:11:46 -07:00
M0stafaRady	add4c5f6c8	Adding cocotb evironment with tests and scripts to run	2022-09-30 03:52:34 -07:00