riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/verilog/rtl/caravel.v

1634 lines
49 KiB
Coq
Raw Normal View History

fixes for RTL testbenches with mgmt core wrapper
2021-12-05 12:11:10 -06:00
`ifdef SIM
`default_nettype wire
`endif
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
/*--------------------------------------------------------------*/
/* caravel, a project harness for the Google/SkyWater sky130 */
/* fabrication process and open source PDK */
/* */
/* Copyright 2020 efabless, Inc. */
/* Written by Tim Edwards, December 2019 */
/* and Mohamed Shalan, August 2020 */
/* This file is open source hardware released under the */
/* Apache 2.0 license. See file LICENSE. */
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
/* */
/* Updated 10/15/2021: Revised using the housekeeping module */
/* from housekeeping.v (refactoring a number of functions from */
/* the management SoC). */
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
/* */
/*--------------------------------------------------------------*/
module caravel (
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// All top-level I/O are package-facing pins
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
inout vddio, // Common 3.3V padframe/ESD power
inout vddio_2, // Common 3.3V padframe/ESD power
inout vssio, // Common padframe/ESD ground
inout vssio_2, // Common padframe/ESD ground
inout vdda, // Management 3.3V power
inout vssa, // Common analog ground
inout vccd, // Management/Common 1.8V power
inout vssd, // Common digital ground
inout vdda1, // User area 1 3.3V power
inout vdda1_2, // User area 1 3.3V power
inout vdda2, // User area 2 3.3V power
inout vssa1, // User area 1 analog ground
inout vssa1_2, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V power
inout vccd2, // User area 2 1.8V power
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
inout gpio, // Used for external LDO control
inout [`MPRJ_IO_PADS-1:0] mprj_io,
input clock, // CMOS core clock input, not a crystal
input resetb, // Reset input (sense inverted)
// Note that only two flash data pins are dedicated to the
// management SoC wrapper. The management SoC exports the
// quad SPI mode status to make use of the top two mprj_io
// pins for io2 and io3.
output flash_csb,
output flash_clk,
output flash_io0,
output flash_io1
);
//------------------------------------------------------------
// This value is uniquely defined for each user project.
//------------------------------------------------------------
parameter USER_PROJECT_ID = 32'h00000000;
/*
*--------------------------------------------------------------------
*
* These pins are overlaid on mprj_io space. They have the function
* below when the management processor is in reset, or in the default
* configuration. They are assigned to uses in the user space by the
* configuration program running off of the SPI flash. Note that even
* when the user has taken control of these pins, they can be restored
* to the original use by setting the resetb pin low. The SPI pins and
* UART pins can be connected directly to an FTDI chip as long as the
* FTDI chip sets these lines to high impedence (input function) at
* all times except when holding the chip in reset.
*
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
* JTAG = mprj_io[0] (inout)
* SDO = mprj_io[1] (output)
* SDI = mprj_io[2] (input)
* CSB = mprj_io[3] (input)
* SCK = mprj_io[4] (input)
* ser_rx = mprj_io[5] (input)
* ser_tx = mprj_io[6] (output)
* irq = mprj_io[7] (input)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
*
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
* spi_sck = mprj_io[32] (output)
* spi_csb = mprj_io[33] (output)
* spi_sdi = mprj_io[34] (input)
* spi_sdo = mprj_io[35] (output)
* flash_io2 = mprj_io[36] (inout)
* flash_io3 = mprj_io[37] (inout)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
*
* These pins are reserved for any project that wants to incorporate
* its own processor and flash controller. While a user project can
* technically use any available I/O pins for the purpose, these
* four pins connect to a pass-through mode from the SPI slave (pins
* 1-4 above) so that any SPI flash connected to these specific pins
* can be accessed through the SPI slave even when the processor is in
* reset.
*
* user_flash_csb = mprj_io[8]
* user_flash_sck = mprj_io[9]
* user_flash_io0 = mprj_io[10]
* user_flash_io1 = mprj_io[11]
*
*--------------------------------------------------------------------
*/
// One-bit GPIO dedicated to management SoC (outside of user control)
wire gpio_out_core;
wire gpio_in_core;
wire gpio_mode0_core;
wire gpio_mode1_core;
wire gpio_outenb_core;
wire gpio_inenb_core;
// User Project Control (pad-facing)
wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
wire [`MPRJ_IO_PADS-1:0] mprj_io_one;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// User Project Control (user-facing)
wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
wire [`MPRJ_IO_PADS-1:0] user_io_in;
wire [`MPRJ_IO_PADS-1:0] user_io_out;
wire [`MPRJ_IO_PADS-10:0] user_analog_io;
/* Padframe control signals */
wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
wire mprj_io_loader_resetn;
wire mprj_io_loader_clock;
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
wire mprj_io_loader_strobe;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire mprj_io_loader_data_1; /* user1 side serial loader */
wire mprj_io_loader_data_2; /* user2 side serial loader */
// User Project Control management I/O
// There are two types of GPIO connections:
// (1) Full Bidirectional: Management connects to in, out, and oeb
// Uses: JTAG and SDO
// (2) Selectable bidirectional: Management connects to in and out,
// which are tied together. oeb is grounded (oeb from the
// configuration is used)
// SDI = mprj_io[2] (input)
// CSB = mprj_io[3] (input)
// SCK = mprj_io[4] (input)
// ser_rx = mprj_io[5] (input)
// ser_tx = mprj_io[6] (output)
// irq = mprj_io[7] (input)
Added buffers to the top level, inside a macro called gpio_signal_buffering (gpio_signal_buffering_alt in caravan). Note that this macro requires manual placement and routing, like the padframe, and the top level will need to route around its own internal routes.
2022-10-13 12:29:27 -05:00
wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* two- and three-pin data in */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_out; /* two- and three-pin data out */
Corrected a typo in the definition of the mgmt_io_oeb vector in caravel.v, which should be the same as mgmt_io_in and mgmt_io_out and should equal the number of user I/O pads (38).
2022-10-05 19:52:21 -05:00
wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb; /* output enable, used only by */
Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01).
2022-10-05 09:02:24 -05:00
/* the three-pin interfaces */
Several more LVS corrections, including fixing a label in chip_io that got removed from its net by a chang in the LEF view of an I/O pad, and a lack of declaration of an array to attach to pwr_ctrl_out in the verilog, which is valid verilog but netgen can't know the bus size without the no-connect net being declared. The remaining issue has to do with separation of ground domains in the mgmt_protect block.
2021-11-21 21:58:39 -06:00
wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */
update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213
2022-10-14 17:02:16 -05:00
Added buffers to the top level, inside a macro called gpio_signal_buffering (gpio_signal_buffering_alt in caravan). Note that this macro requires manual placement and routing, like the padframe, and the top level will need to route around its own internal routes.
2022-10-13 12:29:27 -05:00
/* Buffers are placed between housekeeping and gpio_control_block */
update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213
2022-10-14 17:02:16 -05:00
/* instances to mitigate timing issues on very long (> 1.5mm) wires. */
Added buffers to the top level, inside a macro called gpio_signal_buffering (gpio_signal_buffering_alt in caravan). Note that this macro requires manual placement and routing, like the padframe, and the top level will need to route around its own internal routes.
2022-10-13 12:29:27 -05:00
wire [`MPRJ_IO_PADS-1:0] mgmt_io_in_hk; /* mgmt_io_in at housekeeping */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_out_hk; /* mgmt_io_out at housekeeping */
wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb_hk; /* mgmt_io_oeb at housekeeping */
Merge branch 'caravel_redesign' into add_top_level_buffers
2022-10-14 17:28:14 -05:00
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire clock_core;
// Power-on-reset signal. The reset pad generates the sense-inverted
// reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
// derived.
wire porb_h;
wire porb_l;
wire por_l;
wire rstb_h;
wire rstb_l;
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Flash SPI communication (management SoC to housekeeping)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire flash_clk_core, flash_csb_core;
wire flash_clk_oeb_core, flash_csb_oeb_core;
wire flash_io0_oeb_core, flash_io1_oeb_core;
wire flash_io2_oeb_core, flash_io3_oeb_core;
wire flash_io0_ieb_core, flash_io1_ieb_core;
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
wire flash_io2_ieb_core, flash_io3_ieb_core;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire flash_io0_do_core, flash_io1_do_core;
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
wire flash_io2_do_core, flash_io3_do_core;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire flash_io0_di_core, flash_io1_di_core;
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
wire flash_io2_di_core, flash_io3_di_core;
// Flash SPI communication (
wire flash_clk_frame;
wire flash_csb_frame;
wire flash_clk_oeb, flash_csb_oeb;
wire flash_clk_ieb, flash_csb_ieb;
wire flash_io0_oeb, flash_io1_oeb;
wire flash_io0_ieb, flash_io1_ieb;
wire flash_io0_do, flash_io1_do;
wire flash_io0_di, flash_io1_di;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
// Flash buffered signals
wire flash_clk_frame_buf;
wire flash_csb_frame_buf;
wire flash_clk_ieb_buf, flash_csb_ieb_buf;
wire flash_io0_oeb_buf, flash_io1_oeb_buf;
wire flash_io0_ieb_buf, flash_io1_ieb_buf;
wire flash_io0_do_buf, flash_io1_do_buf;
wire flash_io0_di_buf, flash_io1_di_buf;
// Clock and reset buffered signals
wire caravel_clk_buf;
wire caravel_rstn_buf;
wire clock_core_buf;
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
// SoC pass through buffered signals
wire mprj_io_loader_clock_buf;
wire mprj_io_loader_strobe_buf;
wire mprj_io_loader_resetn_buf;
wire mprj_io_loader_data_2_buf;
wire rstb_l_buf;
wire por_l_buf;
wire porb_h_buf;
// top-level buffers
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
buff_flash_clkrst flash_clkrst_buffers (
added power connection to buffer top level rtl
2022-10-15 04:27:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
.in_n({
caravel_clk,
caravel_rstn,
flash_clk_frame,
flash_csb_frame,
flash_clk_oeb,
flash_csb_oeb,
flash_io0_oeb,
flash_io1_oeb,
flash_io0_ieb,
flash_io1_ieb,
flash_io0_do,
flash_io1_do }),
.in_s({
clock_core,
flash_io1_di,
flash_io0_di }),
.out_s({
caravel_clk_buf,
caravel_rstn_buf,
flash_clk_frame_buf,
flash_csb_frame_buf,
flash_clk_oeb_buf,
flash_csb_oeb_buf,
flash_io0_oeb_buf,
flash_io1_oeb_buf,
flash_io0_ieb_buf,
flash_io1_ieb_buf,
flash_io0_do_buf,
flash_io1_do_buf }),
.out_n({
clock_core_buf,
flash_io1_di_buf,
flash_io0_di_buf })
);
update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213
2022-10-14 17:02:16 -05:00
`ifdef NO_TOP_LEVEL_BUFFERING
assign mgmt_io_in_hk = mgmt_io_in;
assign mgmt_io_out = mgmt_io_out_hk;
assign mgmt_io_oeb = mgmt_io_oeb_hk;
`else
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
/* NOTE: The first 7 GPIO are unbuffered, and all
* OEB lines except the last three are unbuffered
* (most of these end up being no-connects from
* housekeeping).
*/
assign mgmt_io_in_hk[6:0] = mgmt_io_in[6:0];
assign mgmt_io_out[6:0] = mgmt_io_out_hk[6:0];
assign mgmt_io_oeb[34:0] = mgmt_io_oeb_hk[34:0];
update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213
2022-10-14 17:02:16 -05:00
gpio_signal_buffering sigbuf (
`ifdef USE_POWER_PINS
update caravel top-level rtl to not buffer `porb_h` through the `mgmt_core_wrapper`
2022-10-17 12:46:31 -05:00
.vccd(vccd_core),
.vssd(vssd_core),
update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213
2022-10-14 17:02:16 -05:00
`endif
Once again. . . Rewrote the RTL verilog so that only signals being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
2022-10-16 11:49:44 -05:00
.mgmt_io_in_unbuf(mgmt_io_in[37:7]),
.mgmt_io_out_unbuf(mgmt_io_out_hk[37:7]),
.mgmt_io_oeb_unbuf(mgmt_io_oeb_hk[37:35]),
.mgmt_io_in_buf(mgmt_io_in_hk[37:7]),
.mgmt_io_out_buf(mgmt_io_out[37:7]),
.mgmt_io_oeb_buf(mgmt_io_oeb[37:35])
update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213
2022-10-14 17:02:16 -05:00
);
`endif
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
chip_io padframe(
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`ifndef TOP_ROUTING
// Package Pins
.vddio_pad (vddio), // Common padframe/ESD supply
.vddio_pad2 (vddio_2),
.vssio_pad (vssio), // Common padframe/ESD ground
.vssio_pad2 (vssio_2),
.vccd_pad (vccd), // Common 1.8V supply
.vssd_pad (vssd), // Common digital ground
.vdda_pad (vdda), // Management analog 3.3V supply
.vssa_pad (vssa), // Management analog ground
.vdda1_pad (vdda1), // User area 1 3.3V supply
.vdda1_pad2 (vdda1_2),
.vdda2_pad (vdda2), // User area 2 3.3V supply
.vssa1_pad (vssa1), // User area 1 analog ground
.vssa1_pad2 (vssa1_2),
.vssa2_pad (vssa2), // User area 2 analog ground
.vccd1_pad (vccd1), // User area 1 1.8V supply
.vccd2_pad (vccd2), // User area 2 1.8V supply
.vssd1_pad (vssd1), // User area 1 digital ground
.vssd2_pad (vssd2), // User area 2 digital ground
some rtl changes - remove unused port in chip_io - move the rest of chip_io power ports to the USE_POWER_PINS guard - add caravel_power_routing cell guarded by TOP_ROUTING ifdef
2022-10-10 07:13:48 -05:00
.vddio (vddio_core),
.vssio (vssio_core),
.vdda (vdda_core),
.vssa (vssa_core),
.vccd (vccd_core),
.vssd (vssd_core),
.vdda1 (vdda1_core),
.vdda2 (vdda2_core),
.vssa1 (vssa1_core),
.vssa2 (vssa2_core),
.vccd1 (vccd1_core),
.vccd2 (vccd2_core),
.vssd1 (vssd1_core),
.vssd2 (vssd2_core),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif
// Core Side Pins
.gpio(gpio),
.mprj_io(mprj_io),
.clock(clock),
.resetb(resetb),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
// SoC Core Interface
update caravel top-level rtl to not buffer `porb_h` through the `mgmt_core_wrapper`
2022-10-17 12:46:31 -05:00
.porb_h(porb_h),
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
.por(por_l_buf),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.resetb_core_h(rstb_h),
.clock_core(clock_core),
.gpio_out_core(gpio_out_core),
.gpio_in_core(gpio_in_core),
.gpio_mode0_core(gpio_mode0_core),
.gpio_mode1_core(gpio_mode1_core),
.gpio_outenb_core(gpio_outenb_core),
.gpio_inenb_core(gpio_inenb_core),
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
.flash_csb_core(flash_csb_frame_buf),
.flash_clk_core(flash_clk_frame_buf),
.flash_csb_oeb_core(flash_csb_oeb_buf),
.flash_clk_oeb_core(flash_clk_oeb_buf),
.flash_io0_oeb_core(flash_io0_oeb_buf),
.flash_io1_oeb_core(flash_io1_oeb_buf),
.flash_io0_ieb_core(flash_io0_ieb_buf),
.flash_io1_ieb_core(flash_io1_ieb_buf),
.flash_io0_do_core(flash_io0_do_buf),
.flash_io1_do_core(flash_io1_do_buf),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.flash_io0_di_core(flash_io0_di),
.flash_io1_di_core(flash_io1_di),
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.mprj_io_one(mprj_io_one),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.mprj_io_in(mprj_io_in),
.mprj_io_out(mprj_io_out),
.mprj_io_oeb(mprj_io_oeb),
.mprj_io_inp_dis(mprj_io_inp_dis),
.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
.mprj_io_vtrip_sel(mprj_io_vtrip_sel),
.mprj_io_slow_sel(mprj_io_slow_sel),
.mprj_io_holdover(mprj_io_holdover),
.mprj_io_analog_en(mprj_io_analog_en),
.mprj_io_analog_sel(mprj_io_analog_sel),
.mprj_io_analog_pol(mprj_io_analog_pol),
.mprj_io_dm(mprj_io_dm),
.mprj_analog_io(user_analog_io)
);
// SoC core
wire caravel_clk;
wire caravel_clk2;
wire caravel_rstn;
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
// Logic analyzer signals
wire [127:0] la_data_in_user; // From CPU to MPRJ
wire [127:0] la_data_in_mprj; // From MPRJ to CPU
wire [127:0] la_data_out_mprj; // From CPU to MPRJ
wire [127:0] la_data_out_user; // From MPRJ to CPU
wire [127:0] la_oenb_user; // From CPU to MPRJ
wire [127:0] la_oenb_mprj; // From CPU to MPRJ
wire [127:0] la_iena_mprj; // From CPU only
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
wire [2:0] user_irq; // From MRPJ to CPU
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire [2:0] user_irq_core;
wire [2:0] user_irq_ena;
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
wire [2:0] irq_spi; // From SPI and external pins
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Exported Wishbone Bus (processor facing)
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
wire mprj_iena_wb;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire mprj_cyc_o_core;
wire mprj_stb_o_core;
wire mprj_we_o_core;
wire [3:0] mprj_sel_o_core;
wire [31:0] mprj_adr_o_core;
wire [31:0] mprj_dat_o_core;
wire mprj_ack_i_core;
wire [31:0] mprj_dat_i_core;
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
wire [31:0] hk_dat_i;
wire hk_ack_i;
wire hk_stb_o;
This (late and invasive) change modifies the housekeeping block to add a separate signal for the houskeeping wb_cyc_i wishbone signal, instead of combining it with the user project's wb_cyc_i. This change makes it compatible with the LiteX implementation of the wishbone bus.
2021-11-29 13:23:30 -06:00
wire hk_cyc_o;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Exported Wishbone Bus (user area facing)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire mprj_cyc_o_user;
wire mprj_stb_o_user;
wire mprj_we_o_user;
wire [3:0] mprj_sel_o_user;
wire [31:0] mprj_adr_o_user;
wire [31:0] mprj_dat_o_user;
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
wire [31:0] mprj_dat_i_user;
wire mprj_ack_i_user;
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Mask revision
wire [31:0] mask_rev;
wire mprj_clock;
wire mprj_clock2;
wire mprj_reset;
// Power monitoring
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire mprj_vcc_pwrgood;
wire mprj2_vcc_pwrgood;
wire mprj_vdd_pwrgood;
wire mprj2_vdd_pwrgood;
Remove SRAM read-only interface (#151) * Removed the SRAM read-only interface by wrapping all related code in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:23:07 -05:00
`ifdef USE_SRAM_RO_INTERFACE
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
// SRAM read-only access from housekeeping
Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and storage. Not all of these pass simulation checks. Added back the bit-bang control of the GPIO programming. Added back the read-only interface between the housekeeping module and the SRAM 2nd port. Revised the memory map text document to reflect the addition of the SRAM ports. There is not yet a testbench for the SRAM read-only interface.
2021-10-19 18:05:47 -05:00
wire hkspi_sram_clk;
wire hkspi_sram_csb;
wire [7:0] hkspi_sram_addr;
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
wire [31:0] hkspi_sram_data;
Remove SRAM read-only interface (#151) * Removed the SRAM read-only interface by wrapping all related code in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:23:07 -05:00
`endif
Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and storage. Not all of these pass simulation checks. Added back the bit-bang control of the GPIO programming. Added back the read-only interface between the housekeeping module and the SRAM 2nd port. Revised the memory map text document to reflect the addition of the SRAM ports. There is not yet a testbench for the SRAM read-only interface.
2021-10-19 18:05:47 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Management processor (wrapper). Any management core
// implementation must match this pinout.
152 add pass thru for clock and reset (#154) * update caravel.v and caravan.v for clock and reset passthru. * Apply automatic changes to Manifest and README.rst * Apply automatic changes to Manifest and README.rst Co-authored-by: jeffdi <jeffdi@users.noreply.github.com> Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu> Co-authored-by: shalan <shalan@users.noreply.github.com>
2022-10-07 03:36:26 -05:00
// Pass thru clock and reset
wire clk_passthru;
wire resetn_passthru;
update caravel top-level rtl to not buffer `porb_h` through the `mgmt_core_wrapper`
2022-10-17 12:46:31 -05:00
// NC passthru signal porb_h
wire porb_h_in_nc;
wire porb_h_out_nc;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
mgmt_core_wrapper soc (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
// SoC pass through buffered signals
.serial_clock_in(mprj_io_loader_clock),
.serial_clock_out(mprj_io_loader_clock_buf),
.serial_load_in(mprj_io_loader_strobe),
.serial_load_out(mprj_io_loader_strobe_buf),
.serial_resetn_in(mprj_io_loader_resetn),
.serial_resetn_out(mprj_io_loader_resetn_buf),
.serial_data_2_in(mprj_io_loader_data_2),
.serial_data_2_out(mprj_io_loader_data_2_buf),
.rstb_l_in(rstb_l),
.rstb_l_out(rstb_l_buf),
update caravel top-level rtl to not buffer `porb_h` through the `mgmt_core_wrapper`
2022-10-17 12:46:31 -05:00
.porb_h_in(porb_h_in_nc),
.porb_h_out(porb_h_out_nc),
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
.por_l_in(por_l),
.por_l_out(por_l_buf),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Clock and reset
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
.core_clk(caravel_clk_buf),
.core_rstn(caravel_rstn_buf),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
152 add pass thru for clock and reset (#154) * update caravel.v and caravan.v for clock and reset passthru. * Apply automatic changes to Manifest and README.rst * Apply automatic changes to Manifest and README.rst Co-authored-by: jeffdi <jeffdi@users.noreply.github.com> Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu> Co-authored-by: shalan <shalan@users.noreply.github.com>
2022-10-07 03:36:26 -05:00
// Pass thru Clock and reset
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
.clk_in(caravel_clk_buf),
.resetn_in(caravel_rstn_buf),
152 add pass thru for clock and reset (#154) * update caravel.v and caravan.v for clock and reset passthru. * Apply automatic changes to Manifest and README.rst * Apply automatic changes to Manifest and README.rst Co-authored-by: jeffdi <jeffdi@users.noreply.github.com> Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu> Co-authored-by: shalan <shalan@users.noreply.github.com>
2022-10-07 03:36:26 -05:00
.clk_out(clk_passthru),
.resetn_out(resetn_passthru),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// GPIO (1 pin)
.gpio_out_pad(gpio_out_core),
.gpio_in_pad(gpio_in_core),
.gpio_mode0_pad(gpio_mode0_core),
.gpio_mode1_pad(gpio_mode1_core),
.gpio_outenb_pad(gpio_outenb_core),
.gpio_inenb_pad(gpio_inenb_core),
// Primary SPI flash controller
.flash_csb(flash_csb_core),
.flash_clk(flash_clk_core),
Additional corrections, mostly to the housekeeping module. The top-level simulation now passes the GPIO testbench.
2021-10-17 20:38:40 -05:00
.flash_io0_oeb(flash_io0_oeb_core),
.flash_io0_di(flash_io0_di_core),
.flash_io0_do(flash_io0_do_core),
.flash_io1_oeb(flash_io1_oeb_core),
.flash_io1_di(flash_io1_di_core),
.flash_io1_do(flash_io1_do_core),
.flash_io2_oeb(flash_io2_oeb_core),
.flash_io2_di(flash_io2_di_core),
.flash_io2_do(flash_io2_do_core),
.flash_io3_oeb(flash_io3_oeb_core),
.flash_io3_di(flash_io3_di_core),
.flash_io3_do(flash_io3_do_core),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Exported Wishbone Bus
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
.mprj_wb_iena(mprj_iena_wb),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.mprj_cyc_o(mprj_cyc_o_core),
.mprj_stb_o(mprj_stb_o_core),
.mprj_we_o(mprj_we_o_core),
.mprj_sel_o(mprj_sel_o_core),
.mprj_adr_o(mprj_adr_o_core),
.mprj_dat_o(mprj_dat_o_core),
.mprj_ack_i(mprj_ack_i_core),
.mprj_dat_i(mprj_dat_i_core),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.hk_stb_o(hk_stb_o),
This (late and invasive) change modifies the housekeeping block to add a separate signal for the houskeeping wb_cyc_i wishbone signal, instead of combining it with the user project's wb_cyc_i. This change makes it compatible with the LiteX implementation of the wishbone bus.
2021-11-29 13:23:30 -06:00
.hk_cyc_o(hk_cyc_o),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.hk_dat_i(hk_dat_i),
.hk_ack_i(hk_ack_i),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// IRQ
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.irq({irq_spi, user_irq}),
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
.user_irq_ena(user_irq_ena),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Module status (these may or may not be implemented)
.qspi_enabled(qspi_enabled),
.uart_enabled(uart_enabled),
.spi_enabled(spi_enabled),
.debug_mode(debug_mode),
// Module I/O (these may or may not be implemented)
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
// UART
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.ser_tx(ser_tx),
.ser_rx(ser_rx),
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
// SPI master
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.spi_sdi(spi_sdi),
.spi_csb(spi_csb),
.spi_sck(spi_sck),
.spi_sdo(spi_sdo),
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.spi_sdoenb(spi_sdoenb),
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
// Debug
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.debug_in(debug_in),
.debug_out(debug_out),
.debug_oeb(debug_oeb),
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
// Logic analyzer
.la_input(la_data_in_mprj),
.la_output(la_data_out_mprj),
.la_oenb(la_oenb_mprj),
.la_iena(la_iena_mprj),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Remove SRAM read-only interface (#151) * Removed the SRAM read-only interface by wrapping all related code in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:23:07 -05:00
`ifdef USE_SRAM_RO_INTERFACE
Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and storage. Not all of these pass simulation checks. Added back the bit-bang control of the GPIO programming. Added back the read-only interface between the housekeeping module and the SRAM 2nd port. Revised the memory map text document to reflect the addition of the SRAM ports. There is not yet a testbench for the SRAM read-only interface.
2021-10-19 18:05:47 -05:00
// SRAM Read-only access from housekeeping
Changed the SRAM read-only port signal names to match the change made to the management SoC wrapper definition---this is just making the nomenclature better (no functional change).
2021-10-22 10:51:07 -05:00
.sram_ro_clk(hkspi_sram_clk),
.sram_ro_csb(hkspi_sram_csb),
.sram_ro_addr(hkspi_sram_addr),
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.sram_ro_data(hkspi_sram_data),
Remove SRAM read-only interface (#151) * Removed the SRAM read-only interface by wrapping all related code in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:23:07 -05:00
`endif
Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and storage. Not all of these pass simulation checks. Added back the bit-bang control of the GPIO programming. Added back the read-only interface between the housekeeping module and the SRAM 2nd port. Revised the memory map text document to reflect the addition of the SRAM ports. There is not yet a testbench for the SRAM read-only interface.
2021-10-19 18:05:47 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Trap status
.trap(trap)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
);
/* Clock and reset to user space are passed through a tristate */
/* buffer like the above, but since they are intended to be */
/* always active, connect the enable to the logic-1 output from */
/* the vccd1 domain. */
mgmt_protect mgmt_buffers (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),
.vccd1(vccd1_core),
.vssd1(vssd1_core),
.vccd2(vccd2_core),
.vssd2(vssd2_core),
.vdda1(vdda1_core),
.vssa1(vssa1_core),
.vdda2(vdda2_core),
.vssa2(vssa2_core),
`endif
152 add pass thru for clock and reset (#154) * update caravel.v and caravan.v for clock and reset passthru. * Apply automatic changes to Manifest and README.rst * Apply automatic changes to Manifest and README.rst Co-authored-by: jeffdi <jeffdi@users.noreply.github.com> Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu> Co-authored-by: shalan <shalan@users.noreply.github.com>
2022-10-07 03:36:26 -05:00
.caravel_clk(clk_passthru),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.caravel_clk2(caravel_clk2),
152 add pass thru for clock and reset (#154) * update caravel.v and caravan.v for clock and reset passthru. * Apply automatic changes to Manifest and README.rst * Apply automatic changes to Manifest and README.rst Co-authored-by: jeffdi <jeffdi@users.noreply.github.com> Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu> Co-authored-by: shalan <shalan@users.noreply.github.com>
2022-10-07 03:36:26 -05:00
.caravel_rstn(resetn_passthru),
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
.mprj_iena_wb(mprj_iena_wb),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.mprj_cyc_o_core(mprj_cyc_o_core),
.mprj_stb_o_core(mprj_stb_o_core),
.mprj_we_o_core(mprj_we_o_core),
.mprj_sel_o_core(mprj_sel_o_core),
.mprj_adr_o_core(mprj_adr_o_core),
.mprj_dat_o_core(mprj_dat_o_core),
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
.mprj_ack_i_core(mprj_ack_i_core),
.mprj_dat_i_core(mprj_dat_i_core),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.user_irq_core(user_irq_core),
.user_irq_ena(user_irq_ena),
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
.la_data_out_core(la_data_out_user),
.la_data_out_mprj(la_data_out_mprj),
Fixed two signals on the mgmt_protect in caravel that got merged and scrambled somehow.
2021-11-17 13:08:47 -06:00
.la_data_in_core(la_data_in_user),
.la_data_in_mprj(la_data_in_mprj),
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
.la_oenb_mprj(la_oenb_mprj),
Fixed another missing line from the management protect block call in caravel.v.
2021-11-18 07:25:13 -06:00
.la_oenb_core(la_oenb_user),
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
.la_iena_mprj(la_iena_mprj),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.user_clock(mprj_clock),
.user_clock2(mprj_clock2),
.user_reset(mprj_reset),
.mprj_cyc_o_user(mprj_cyc_o_user),
.mprj_stb_o_user(mprj_stb_o_user),
.mprj_we_o_user(mprj_we_o_user),
.mprj_sel_o_user(mprj_sel_o_user),
.mprj_adr_o_user(mprj_adr_o_user),
.mprj_dat_o_user(mprj_dat_o_user),
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
.mprj_dat_i_user(mprj_dat_i_user),
.mprj_ack_i_user(mprj_ack_i_user),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.user_irq(user_irq),
.user1_vcc_powergood(mprj_vcc_pwrgood),
.user2_vcc_powergood(mprj2_vcc_pwrgood),
.user1_vdd_powergood(mprj_vdd_pwrgood),
.user2_vdd_powergood(mprj2_vdd_pwrgood)
);
/*--------------------------------------------------*/
/* Wrapper module around the user project */
/*--------------------------------------------------*/
user_project_wrapper mprj (
`ifdef USE_POWER_PINS
.vdda1(vdda1_core), // User area 1 3.3V power
.vdda2(vdda2_core), // User area 2 3.3V power
.vssa1(vssa1_core), // User area 1 analog ground
.vssa2(vssa2_core), // User area 2 analog ground
.vccd1(vccd1_core), // User area 1 1.8V power
.vccd2(vccd2_core), // User area 2 1.8V power
.vssd1(vssd1_core), // User area 1 digital ground
.vssd2(vssd2_core), // User area 2 digital ground
`endif
.wb_clk_i(mprj_clock),
.wb_rst_i(mprj_reset),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Management SoC Wishbone bus (exported)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.wbs_cyc_i(mprj_cyc_o_user),
.wbs_stb_i(mprj_stb_o_user),
.wbs_we_i(mprj_we_o_user),
.wbs_sel_i(mprj_sel_o_user),
.wbs_adr_i(mprj_adr_o_user),
.wbs_dat_i(mprj_dat_o_user),
Revised the management protect block to include protections against an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).
2021-10-27 18:36:43 -05:00
.wbs_ack_o(mprj_ack_i_user),
.wbs_dat_o(mprj_dat_i_user),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// GPIO pad 3-pin interface (plus analog)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.io_in (user_io_in),
.io_out(user_io_out),
.io_oeb(user_io_oeb),
.analog_io(user_analog_io),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Reinstated the logic analyzer as a standard interface for the management SoC.
2021-10-16 16:42:24 -05:00
// Logic analyzer
.la_data_in(la_data_in_user),
.la_data_out(la_data_out_user),
.la_oenb(la_oenb_user),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Independent clock
.user_clock2(mprj_clock2),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// IRQ
.user_irq(user_irq_core)
);
/*------------------------------------------*/
/* End user project instantiation */
/*------------------------------------------*/
wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
mprj_io_loader_data_1};
// Note that serial_link_2 is backwards compared to serial_link_1, so it
// shifts in the other direction.
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2_buf,
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
// Propagating clock and reset to mitigate timing and fanout issues
wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1_shifted;
wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2_shifted;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
mprj_io_loader_clock};
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
assign gpio_clock_2_shifted = {mprj_io_loader_clock_buf,
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
mprj_io_loader_resetn};
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
assign gpio_resetn_2_shifted = {mprj_io_loader_resetn_buf,
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-2:0],
mprj_io_loader_strobe};
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
assign gpio_load_2_shifted = {mprj_io_loader_strobe_buf,
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
gpio_load_2[`MPRJ_IO_PADS_2-1:1]};
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
wire [2:0] spi_pll_sel;
wire [2:0] spi_pll90_sel;
wire [4:0] spi_pll_div;
wire [25:0] spi_pll_trim;
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Clocking control
Corrected the issue reported on the github issue tracker (#34) (#50) * Corrected the issue reported on the github issue tracker (#34) in which the use of "clocking" as an instance name in caravel and caravan conflicts with the system verilog keyword of the same name. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-04-07 09:44:57 -05:00
caravel_clocking clock_ctrl (
[RTL] Move inverter from top level to HK - fixed clock connection to the digital_pll and caravel_clocking - renamed power pins of the HK/caravel_clocking to VPWR/VGND
2021-11-16 05:59:17 -06:00
`ifdef USE_POWER_PINS
[RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection
2021-11-17 05:17:23 -06:00
.VPWR(vccd_core),
.VGND(vssd_core),
[RTL] Move inverter from top level to HK - fixed clock connection to the digital_pll and caravel_clocking - renamed power pins of the HK/caravel_clocking to VPWR/VGND
2021-11-16 05:59:17 -06:00
`endif
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.ext_clk_sel(ext_clk_sel),
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
.ext_clk(clock_core_buf),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.pll_clk(pll_clk),
.pll_clk90(pll_clk90),
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
.resetb(rstb_l_buf),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.sel(spi_pll_sel),
.sel2(spi_pll90_sel),
.ext_reset(ext_reset), // From housekeeping SPI
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.core_clk(caravel_clk),
.user_clk(caravel_clk2),
A number of small corrections.
2021-10-16 22:55:57 -05:00
.resetb_sync(caravel_rstn)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
);
// DCO/Digital Locked Loop
digital_pll pll (
[RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection
2021-11-17 05:17:23 -06:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
update top-level rtl with 7 pass through signals to be buffered inside the SoC
2022-10-14 15:11:42 -05:00
.resetb(rstb_l_buf),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.enable(spi_pll_ena),
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
.osc(clock_core_buf),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.clockp({pll_clk, pll_clk90}),
.div(spi_pll_div),
.dco(spi_pll_dco_ena),
.ext_trim(spi_pll_trim)
);
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
// Housekeeping interface
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
housekeeping housekeeping (
[RTL] Move inverter from top level to HK - fixed clock connection to the digital_pll and caravel_clocking - renamed power pins of the HK/caravel_clocking to VPWR/VGND
2021-11-16 05:59:17 -06:00
`ifdef USE_POWER_PINS
[RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection
2021-11-17 05:17:23 -06:00
.VPWR(vccd_core),
.VGND(vssd_core),
[RTL] Move inverter from top level to HK - fixed clock connection to the digital_pll and caravel_clocking - renamed power pins of the HK/caravel_clocking to VPWR/VGND
2021-11-16 05:59:17 -06:00
`endif
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Corrected the clock signal into the housekeeping module, which was incorrectly assigned to the clock on the user side of the managment protect block, causing it to be undefined when the user area power supply is down. The "hkspi_power" testbench which tests using the housekeeping SPI while the user area power is grounded now works correctly.
2021-11-03 10:30:39 -05:00
.wb_clk_i(caravel_clk),
[RTL] Move inverter from top level to HK - fixed clock connection to the digital_pll and caravel_clocking - renamed power pins of the HK/caravel_clocking to VPWR/VGND
2021-11-16 05:59:17 -06:00
.wb_rstn_i(caravel_rstn),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.wb_adr_i(mprj_adr_o_core),
.wb_dat_i(mprj_dat_o_core),
.wb_sel_i(mprj_sel_o_core),
.wb_we_i(mprj_we_o_core),
This (late and invasive) change modifies the housekeeping block to add a separate signal for the houskeeping wb_cyc_i wishbone signal, instead of combining it with the user project's wb_cyc_i. This change makes it compatible with the LiteX implementation of the wishbone bus.
2021-11-29 13:23:30 -06:00
.wb_cyc_i(hk_cyc_o),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.wb_stb_i(hk_stb_o),
.wb_ack_o(hk_ack_i),
.wb_dat_o(hk_dat_i),
A number of small corrections.
2021-10-16 22:55:57 -05:00
.porb(porb_l),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.pll_ena(spi_pll_ena),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.pll_dco_ena(spi_pll_dco_ena),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.pll_div(spi_pll_div),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.pll_sel(spi_pll_sel),
.pll90_sel(spi_pll90_sel),
.pll_trim(spi_pll_trim),
.pll_bypass(ext_clk_sel),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.qspi_enabled(qspi_enabled),
.uart_enabled(uart_enabled),
.spi_enabled(spi_enabled),
.debug_mode(debug_mode),
.ser_tx(ser_tx),
.ser_rx(ser_rx),
.spi_sdi(spi_sdi),
.spi_csb(spi_csb),
.spi_sck(spi_sck),
.spi_sdo(spi_sdo),
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.spi_sdoenb(spi_sdoenb),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.debug_in(debug_in),
.debug_out(debug_out),
.debug_oeb(debug_oeb),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.irq(irq_spi),
.reset(ext_reset),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
A number of small corrections.
2021-10-16 22:55:57 -05:00
.serial_clock(mprj_io_loader_clock),
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
.serial_load(mprj_io_loader_strobe),
A number of small corrections.
2021-10-16 22:55:57 -05:00
.serial_resetn(mprj_io_loader_resetn),
.serial_data_1(mprj_io_loader_data_1),
.serial_data_2(mprj_io_loader_data_2),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
update top-level rtl to resolve conflict with adding top level buffers between housekeeping and `gpio_control_block` https://github.com/efabless/caravel/pull/213
2022-10-14 17:02:16 -05:00
.mgmt_gpio_in(mgmt_io_in_hk),
.mgmt_gpio_out(mgmt_io_out_hk),
.mgmt_gpio_oeb(mgmt_io_oeb_hk),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Several more LVS corrections, including fixing a label in chip_io that got removed from its net by a chang in the LEF view of an I/O pad, and a lack of declaration of an array to attach to pwr_ctrl_out in the verilog, which is valid verilog but netgen can't know the bus size without the no-connect net being declared. The remaining issue has to do with separation of ground domains in the mgmt_protect block.
2021-11-21 21:58:39 -06:00
.pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.trap(trap),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
A handful of changes/corrections: (1) Housekeeping signal "user_clock" (input for monitoring) changed from being connected directly to the user project (where it shouldn't be) to the same signal on the input side of the management protect block (where it should be). This is functionally the same. Checked for any other signals connected directly from the user project to any block other than mgmt_protect, didn't find any (good). Modified the gate-level netlists and top-level layouts for caravel and caravan with the corresponding change. This was the only change affecting layout. Also: Revised the "pll" testbench. This is still ongoing work. Also: Fixed the way the pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so that it isn't so bizarre. Most of this change is functionally agnostic (just a change in the way the ifdefs work), but did fix an incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 18:38:24 -06:00
.user_clock(caravel_clk2),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.mask_rev_in(mask_rev),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.spimemio_flash_csb(flash_csb_core),
.spimemio_flash_clk(flash_clk_core),
.spimemio_flash_io0_oeb(flash_io0_oeb_core),
.spimemio_flash_io1_oeb(flash_io1_oeb_core),
.spimemio_flash_io2_oeb(flash_io2_oeb_core),
.spimemio_flash_io3_oeb(flash_io3_oeb_core),
.spimemio_flash_io0_do(flash_io0_do_core),
.spimemio_flash_io1_do(flash_io1_do_core),
.spimemio_flash_io2_do(flash_io2_do_core),
.spimemio_flash_io3_do(flash_io3_do_core),
.spimemio_flash_io0_di(flash_io0_di_core),
.spimemio_flash_io1_di(flash_io1_di_core),
.spimemio_flash_io2_di(flash_io2_di_core),
.spimemio_flash_io3_di(flash_io3_di_core),
.pad_flash_csb(flash_csb_frame),
.pad_flash_csb_oeb(flash_csb_oeb),
.pad_flash_clk(flash_clk_frame),
.pad_flash_clk_oeb(flash_clk_oeb),
.pad_flash_io0_oeb(flash_io0_oeb),
.pad_flash_io1_oeb(flash_io1_oeb),
.pad_flash_io0_ieb(flash_io0_ieb),
.pad_flash_io1_ieb(flash_io1_ieb),
.pad_flash_io0_do(flash_io0_do),
.pad_flash_io1_do(flash_io1_do),
update caravel top-level rtl to add `buff_flash_clkrst` module
2022-10-13 14:11:22 -05:00
.pad_flash_io0_di(flash_io0_di_buf),
.pad_flash_io1_di(flash_io1_di_buf),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
Remove SRAM read-only interface (#151) * Removed the SRAM read-only interface by wrapping all related code in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:23:07 -05:00
`ifdef USE_SRAM_RO_INTERFACE
Changed the SRAM read-only port signal names to match the change made to the management SoC wrapper definition---this is just making the nomenclature better (no functional change).
2021-10-22 10:51:07 -05:00
.sram_ro_clk(hkspi_sram_clk),
.sram_ro_csb(hkspi_sram_csb),
.sram_ro_addr(hkspi_sram_addr),
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.sram_ro_data(hkspi_sram_data),
Remove SRAM read-only interface (#151) * Removed the SRAM read-only interface by wrapping all related code in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:23:07 -05:00
`endif
Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and storage. Not all of these pass simulation checks. Added back the bit-bang control of the GPIO programming. Added back the read-only interface between the housekeeping module and the SRAM 2nd port. Revised the memory map text document to reflect the addition of the SRAM ports. There is not yet a testbench for the SRAM read-only interface.
2021-10-19 18:05:47 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
.usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
);
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
/* GPIO defaults (via programmed) */
wire [`MPRJ_IO_PADS*13-1:0] gpio_defaults;
/* Fixed defaults for the first 5 GPIO pins */
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h1803)
Made modifications in support of changing the hard-coded default configuration of GPIO 3 (CSB) from a standard input to a weak pull-up input.
2022-09-27 19:58:57 -05:00
) gpio_defaults_block_0 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
Made modifications in support of changing the hard-coded default configuration of GPIO 3 (CSB) from a standard input to a weak pull-up input.
2022-09-27 19:58:57 -05:00
.gpio_defaults(gpio_defaults[12:0])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h1803)
) gpio_defaults_block_1 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[25:13])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0403)
) gpio_defaults_block_2 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[38:26])
);
// CSB pin is set as an internal pull-up
gpio_defaults_block #(
Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01).
2022-10-05 09:02:24 -05:00
.GPIO_CONFIG_INIT(13'h0801)
Made modifications in support of changing the hard-coded default configuration of GPIO 3 (CSB) from a standard input to a weak pull-up input.
2022-09-27 19:58:57 -05:00
) gpio_defaults_block_3 (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[51:39])
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(13'h0403)
Made modifications in support of changing the hard-coded default configuration of GPIO 3 (CSB) from a standard input to a weak pull-up input.
2022-09-27 19:58:57 -05:00
) gpio_defaults_block_4 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
Made modifications in support of changing the hard-coded default configuration of GPIO 3 (CSB) from a standard input to a weak pull-up input.
2022-09-27 19:58:57 -05:00
.gpio_defaults(gpio_defaults[64:52])
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
);
/* Via-programmable defaults for the rest of the GPIO pins */
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_5 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[77:65])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_6 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[90:78])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_7 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[103:91])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_8 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[116:104])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_9 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[129:117])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_10 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[142:130])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_11 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[155:143])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_12 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[168:156])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_13 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[181:169])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_14 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[194:182])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_15_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_15 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[207:195])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_16_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_16 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[220:208])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_17_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_17 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[233:221])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_18_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_18 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[246:234])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_19_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_19 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[259:247])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_20_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_20 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[272:260])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_21_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_21 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[285:273])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_22_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_22 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[298:286])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_23_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_23 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[311:299])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_24_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_24 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[324:312])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_25 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[337:325])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_26 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[350:338])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_27 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[363:351])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_28 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[376:364])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_29 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[389:377])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_30 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[402:390])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_31 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[415:403])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_32 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[428:416])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_33 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[441:429])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_34 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[454:442])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_35 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[467:455])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_36 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[480:468])
);
gpio_defaults_block #(
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
Corrected the instance names in the layout so that they once again correspond to what the script gen_gpio_defaults.py is looking for.
2021-11-29 18:57:33 -06:00
) gpio_defaults_block_37 (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.gpio_defaults(gpio_defaults[493:481])
);
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Each control block sits next to an I/O pad in the user area.
// It gets input through a serial chain from the previous control
// block and passes it to the next control block. Due to the nature
// of the shift register, bits are presented in reverse, as the first
// bit in ends up as the last bit of the last I/O pad control block.
// There are two types of block; the first two and the last two
// are configured to be full bidirectional under control of the
// management Soc (JTAG and SDO for the first two; flash_io2 and
// flash_io3 for the last two). The rest are configured to be default
// (input). Note that the first two and last two are the ones closest
// to the management SoC on either side, which minimizes the wire length
// of the extra signals those pads need.
/* First two GPIOs (JTAG and SDO) */
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
gpio_control_block gpio_control_bidir_1 [1:0] (
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`ifdef USE_POWER_PINS
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.vccd(vccd_core),
.vssd(vssd_core),
.vccd1(vccd1_core),
.vssd1(vssd1_core),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.gpio_defaults(gpio_defaults[25:0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Management Soc-facing signals
.resetn(gpio_resetn_1_shifted[1:0]),
.serial_clock(gpio_clock_1_shifted[1:0]),
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
.serial_load(gpio_load_1_shifted[1:0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.resetn_out(gpio_resetn_1[1:0]),
.serial_clock_out(gpio_clock_1[1:0]),
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
.serial_load_out(gpio_load_1[1:0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.mgmt_gpio_in(mgmt_io_in[1:0]),
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.mgmt_gpio_out(mgmt_io_out[1:0]),
.mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.one(mprj_io_one[1:0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.zero(),
// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_1_shifted[1:0]),
.serial_data_out(gpio_serial_link_1[1:0]),
// User-facing signals
.user_gpio_out(user_io_out[1:0]),
.user_gpio_oeb(user_io_oeb[1:0]),
.user_gpio_in(user_io_in[1:0]),
// Pad-facing signals (Pad GPIOv2)
.pad_gpio_inenb(mprj_io_inp_dis[1:0]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
.pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
.pad_gpio_holdover(mprj_io_holdover[1:0]),
.pad_gpio_ana_en(mprj_io_analog_en[1:0]),
.pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
.pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
.pad_gpio_dm(mprj_io_dm[5:0]),
.pad_gpio_outenb(mprj_io_oeb[1:0]),
.pad_gpio_out(mprj_io_out[1:0]),
.pad_gpio_in(mprj_io_in[1:0])
);
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
/* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
gpio_control_block gpio_control_in_1a [5:0] (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),
.vccd1(vccd1_core),
.vssd1(vssd1_core),
`endif
.gpio_defaults(gpio_defaults[103:26]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Management Soc-facing signals
.resetn(gpio_resetn_1_shifted[7:2]),
.serial_clock(gpio_clock_1_shifted[7:2]),
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
.serial_load(gpio_load_1_shifted[7:2]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.resetn_out(gpio_resetn_1[7:2]),
.serial_clock_out(gpio_clock_1[7:2]),
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
.serial_load_out(gpio_load_1[7:2]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.mgmt_gpio_in(mgmt_io_in[7:2]),
Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01).
2022-10-05 09:02:24 -05:00
.mgmt_gpio_out(mgmt_io_out[7:2]),
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.mgmt_gpio_oeb(mprj_io_one[7:2]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.one(mprj_io_one[7:2]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.zero(),
// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_1_shifted[7:2]),
.serial_data_out(gpio_serial_link_1[7:2]),
// User-facing signals
.user_gpio_out(user_io_out[7:2]),
.user_gpio_oeb(user_io_oeb[7:2]),
.user_gpio_in(user_io_in[7:2]),
// Pad-facing signals (Pad GPIOv2)
.pad_gpio_inenb(mprj_io_inp_dis[7:2]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
.pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
.pad_gpio_holdover(mprj_io_holdover[7:2]),
.pad_gpio_ana_en(mprj_io_analog_en[7:2]),
.pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
.pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
.pad_gpio_dm(mprj_io_dm[23:6]),
.pad_gpio_outenb(mprj_io_oeb[7:2]),
.pad_gpio_out(mprj_io_out[7:2]),
.pad_gpio_in(mprj_io_in[7:2])
);
/* Section 1 GPIOs (GPIO 8 to 18) */
gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-9:0] (
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),
.vccd1(vccd1_core),
.vssd1(vssd1_core),
`endif
.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS_1*13-1):104]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Management Soc-facing signals
.resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
.serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
.serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):8]),
.serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):8]),
(1) Corrected an error from a recent commit where the reset was fixed by moving from after the managment protect to before it, but an inversion of the signal was missed, leading to an incorrect wb_rst_i passed to housekeeping. (2) Revised the method to load the serial GPIO data chain from a 2-pin, I2C-like method to a more straightforward 3-pin method with separate reset, clock, and load pins. The load pin propagates through the chaing like the other two. Added a bit-bang signal for the load signal as well. (3) Added an implied buffer after the data output of the GPIO control block to ensure that the data arrives at the next control block after the clock, to prevent hold violations.
2021-11-03 22:18:36 -05:00
.serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).
2021-10-15 20:49:49 -05:00
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01).
2022-10-05 09:02:24 -05:00
.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS_1-1):8]),
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
Merge branch 'caravel_redesign' into make_CSB_a_pullup
2022-10-06 10:39:22 -05:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.one(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.zero(),
// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
.serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):8]),
// User-facing signals
.user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):8]),
.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
.user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):8]),
// Pad-facing signals (Pad GPIOv2)
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):24]),
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):8]),
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):8])
);
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
/* Last three GPIOs (spi_sdo, flash_io2, and flash_io3) */
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
gpio_control_block gpio_control_bidir_2 [2:0] (
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`ifdef USE_POWER_PINS
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.vccd(vccd_core),
.vssd(vssd_core),
.vccd1(vccd1_core),
.vssd1(vssd1_core),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-1):(`MPRJ_IO_PADS*13-39)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Management Soc-facing signals
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01).
2022-10-05 09:02:24 -05:00
.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.mgmt_gpio_oeb(mgmt_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.one(mprj_io_one[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.zero(),
// Serial data chain for pad configuration
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// User-facing signals
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Pad-facing signals (Pad GPIOv2)
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-9)]),
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)])
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
);
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
/* Section 2 GPIOs (GPIO 19 to 34) */
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`ifdef USE_POWER_PINS
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.vccd(vccd_core),
.vssd(vssd_core),
.vccd1(vccd1_core),
.vssd1(vssd1_core),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif
Implemented a system for setting the GPIO power-on defaults through via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.
2021-10-23 16:18:30 -05:00
.gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-40):(`MPRJ_IO_PADS_1*13)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Management Soc-facing signals
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
.resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
.serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
.serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Made updates to correct LVS errors in caravan. Found one major error in the RTL verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.
2021-11-22 21:35:52 -06:00
.resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-4):0]),
.serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-4):0]),
.serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
Corrected the pull-up definition and revised the CSB definition to match the corrected defintions (namely, pull-up is configuration 0x0801, and pull-down is configuration 0x0c01).
2022-10-05 09:02:24 -05:00
.mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
Corrections to the padframe to make sure that all pad digital inputs that are permanently tied low or high come from either the local "TIE" pad connections (if they are in the 3.3V domain) or from a constant one wire in the 1.8V domain that is generated in the gpio_control_block module and exported to the chip_io (or chip_io_alt) module.
2022-09-20 15:00:09 -05:00
.one(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
.zero(),
// Serial data chain for pad configuration
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
.serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-4):0]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// User-facing signals
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.user_gpio_out(user_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.user_gpio_in(user_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
// Pad-facing signals (Pad GPIOv2)
Corrected the last testbenches, added a new testbench for the spi_master since the original one was folded into the sysctrl testbench, but that testbench no longer uses the SPI master. Moved the SPI master from being an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35. Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable from the SPI master can be used.
2021-10-21 18:48:24 -05:00
.pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-10):(`MPRJ_IO_PADS_1*3)]),
.pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)])
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
);
user_id_programming #(
.USER_PROJECT_ID(USER_PROJECT_ID)
) user_id_value (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.mask_rev(mask_rev)
);
// Power-on-reset circuit
simple_por por (
`ifdef USE_POWER_PINS
.vdd3v3(vddio_core),
.vdd1v8(vccd_core),
Final edits to make caravel LVS clean.
2021-11-22 15:51:35 -06:00
.vss3v3(vssio_core),
.vss1v8(vssd_core),
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`endif
.porb_h(porb_h),
.porb_l(porb_l),
.por_l(por_l)
);
// XRES (chip input pin reset) reset level converter
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" cell to the simpler (and easier to remember) "xres_buf".
2021-10-31 20:43:09 -05:00
xres_buf rstb_level (
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
`ifdef USE_POWER_PINS
.VPWR(vddio_core),
.LVPWR(vccd_core),
.LVGND(vssd_core),
.VGND(vssio_core),
`endif
.A(rstb_h),
.X(rstb_l)
);
Added spare logic blocks for GPIO (#153) * Added enough spare logic blocks to have the existing four above the processor, plus one each per GPIO (38 for caravel, 27 for caravan). * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:24:01 -05:00
/* Spare logic for metal mask fixes */
Effectively reverted the change to add spare logic blocks near each (#157) * Effectively reverted the change to add spare logic blocks near each of the GPIO control blocks by changing the definition of NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks) for both caravel and caravan top level RTL verilog modules. * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-10-07 11:28:13 -05:00
// `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4)
`define NUM_SPARE_BLOCKS 4
Added spare logic blocks for GPIO (#153) * Added enough spare logic blocks to have the existing four above the processor, plus one each per GPIO (38 for caravel, 27 for caravan). * Apply automatic changes to Manifest and README.rst Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com> Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-10-07 03:24:01 -05:00
wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
// Four spare logic blocks above the processor and one per GPIO
// control block.
spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
Added a new module with "spare logic" for metal mask fixes.
2021-11-24 08:23:22 -06:00
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),
`endif
Revised the spare logic block to make sure that all inputs are reachable from pins on the boundary once it's synthesized.
2021-11-24 08:34:52 -06:00
.spare_xz(spare_xz_nc),
Added a new module with "spare logic" for metal mask fixes.
2021-11-24 08:23:22 -06:00
.spare_xi(spare_xi_nc),
.spare_xib(spare_xib_nc),
.spare_xna(spare_xna_nc),
.spare_xno(spare_xno_nc),
.spare_xmx(spare_xmx_nc),
.spare_xfq(spare_xfq_nc),
.spare_xfqn(spare_xfqn_nc)
);
some rtl changes - remove unused port in chip_io - move the rest of chip_io power ports to the USE_POWER_PINS guard - add caravel_power_routing cell guarded by TOP_ROUTING ifdef
2022-10-10 07:13:48 -05:00
`ifdef TOP_ROUTING
caravel_power_routing caravel_power_routing();
reharden: caravel ~ reharden with updated pdn ~ add stubs for non functional blocks
2022-10-17 05:59:28 -05:00
copyright_block copyright_block();
caravel_logo caravel_logo();
caravel_motto caravel_motto();
open_source open_source();
user_id_textblock user_id_textblock();
some rtl changes - remove unused port in chip_io - move the rest of chip_io power ports to the USE_POWER_PINS guard - add caravel_power_routing cell guarded by TOP_ROUTING ifdef
2022-10-10 07:13:48 -05:00
`endif
Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).
2021-10-12 15:31:42 -05:00
endmodule
// `default_nettype wire