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Additional corrections, mostly to the housekeeping module. The 

top-level simulation now passes the GPIO testbench.
This commit is contained in:
Tim Edwards 2021-10-17 21:38:40 -04:00
parent 1863a7c529
commit 33ca4e11ef
2 changed files with 524 additions and 518 deletions
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24
verilog/rtl/caravel.v
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@ -371,18 +371,18 @@ module caravel (
// Primary SPI flash controller
.flash_csb(flash_csb_core),
.flash_clk(flash_clk_core),
.flash_io0_oeb(flash_io0_oeb),
.flash_io0_di(flash_io0_di),
.flash_io0_do(flash_io0_do),
.flash_io1_oeb(flash_io1_oeb),
.flash_io1_di(flash_io1_di),
.flash_io1_do(flash_io1_do),
.flash_io2_oeb(flash_io2_oeb),
.flash_io2_di(flash_io2_di),
.flash_io2_do(flash_io2_do),
.flash_io3_oeb(flash_io3_oeb),
.flash_io3_di(flash_io3_di),
.flash_io3_do(flash_io3_do),
.flash_io0_oeb(flash_io0_oeb_core),
.flash_io0_di(flash_io0_di_core),
.flash_io0_do(flash_io0_do_core),
.flash_io1_oeb(flash_io1_oeb_core),
.flash_io1_di(flash_io1_di_core),
.flash_io1_do(flash_io1_do_core),
.flash_io2_oeb(flash_io2_oeb_core),
.flash_io2_di(flash_io2_di_core),
.flash_io2_do(flash_io2_do_core),
.flash_io3_oeb(flash_io3_oeb_core),
.flash_io3_di(flash_io3_di_core),
.flash_io3_do(flash_io3_do_core),
// Exported Wishbone Bus
.mprj_cyc_o(mprj_cyc_o_core),

1018
verilog/rtl/housekeeping.v
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