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588 Commits 16 Branches 1 Tag 1.8 GiB
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588 Commits

Author SHA1 Message Date
Lalit Sharma 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys 2021-01-06 23:19:20 -08:00
tangxifan b3f001c3fa
Merge pull request #81 from lnis-uofu/ql_ap3_arch_eval 
QL specific architecture compatible with AP3
 2021-01-06 11:08:10 -07:00
Tarachand Pagarani 1a4b1bc6b4 Disable generation of formal verification testbench due to disk space 
limitation on github actions.
Disable testcase not fitting on 32x32 device
 2021-01-05 19:44:08 -08:00
Tarachand Pagarani f04e72b5b3 create a copy of cout to connect to regular routing 2020-12-30 06:02:51 -08:00
Tarachand Pagarani 473e1d68a6 fix the carry in dangling 2020-12-29 19:04:56 -08:00
Tarachand Pagarani 61facff870 fix the carry in dangling and carry out accessible to regular routing 2020-12-29 18:54:48 -08:00
Tarachand Pagarani cbe50535ca further changes in architecture to make io interfaces routable 2020-12-28 08:35:17 -08:00
Tarachand Pagarani 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval 2020-12-26 23:57:23 -08:00
Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture 2020-12-26 23:29:13 -08:00
Tarachand Pagarani 1aa0ef68e4 incoporated changes based on feedback from xifan 2020-12-24 23:05:47 -08:00
tangxifan 6428539dcb
Merge pull request #80 from lnis-uofu/ganesh_dev 
Physical design - Critical patch on dangling nets in logic elements
 2020-12-22 08:15:29 -07:00
tangxifan d4b4676ec8
Merge pull request #79 from lnis-uofu/xt_dev 
Critical patch on dangling nets in logic elements
 2020-12-22 08:15:14 -07:00
Ganesh Gore e1a25d61dc [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
Ganesh Gore 562641ed4d [SOFA-CHD] Bugfix to fix floating cin net 2020-12-22 00:23:12 -07:00
tangxifan 6a6b89e7b8 [Arch] Critical patch on dangling nets in logic elements 2020-12-21 22:23:41 -07:00
tangxifan eba3827b77
Merge pull request #78 from lnis-uofu/xt_dev 
Update documentation with latest GDS view
 2020-12-21 13:16:33 -07:00
tangxifan 81a31ea022 [Doc] Update documentation with latest GDS view 2020-12-21 12:37:19 -07:00
Tarachand Pagarani 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback 2020-12-21 07:13:38 -08:00
Ganesh Gore f494c31ca0 [Action] More cleanup while precheck 2020-12-20 17:04:56 -07:00
tangxifan e2c33f1ab3
Merge pull request #77 from lnis-uofu/ganesh_dev 
Updated GDS with chip art  + Cleanup
 2020-12-20 12:11:58 -07:00
Ganesh Gore 6ef27d5399 [Cleanup] Removed old task and verilog directories 2020-12-20 10:50:13 -07:00
Ganesh Gore c36e8d797a Updated all the results 2020-12-20 03:44:00 -07:00
Ganesh Gore 55acf06335 Updated design with new GDS nad updated verilog netlist 2020-12-20 03:31:26 -07:00
Ganesh Gore 5bb8adb448 [Cleanup] Converted .gds to .gds.gz 2020-12-20 02:12:31 -07:00
Ganesh Gore da4ae780a9 [Cleanup] Converted .spef to .spef.gz 2020-12-20 02:10:51 -07:00
Ganesh Gore 694afdf3d0 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-20 02:02:35 -07:00
tangxifan 894378c6a7
Merge pull request #76 from lnis-uofu/xt_dev 
Caravel Testbench for And2_latch benchmark
 2020-12-18 20:59:33 -07:00
tangxifan 82da5dd0b0 [HDL] Update code generator for the changes on custom cell names 2020-12-18 20:25:50 -07:00
tangxifan c523d968c7 [HDL] Bug fix due to custom cell name changing 2020-12-18 20:24:55 -07:00
tangxifan 1eac22feba [Testbench] Critical bug fix on Caravel Testbench: Add a sufficient long waiting time for Caravel to finish its I/O configuration 2020-12-18 20:18:02 -07:00
tangxifan 8a31edb40e [Testbench] Remove compressed testbench file 2020-12-18 19:52:52 -07:00
tangxifan 03316d6e65 [Testbench] Remove signal initialization which is not neccessary for caravel tests 2020-12-18 19:51:54 -07:00
tangxifan e17d51aa9f [Testbench] Bug fix in using power pins 2020-12-18 17:49:16 -07:00
tangxifan e02d830abb Merge branch 'master' into xt_dev 2020-12-18 17:41:33 -07:00
tangxifan f028437fef [Testbench] Update SCFF test to be compatible with simulation with power pins 2020-12-18 16:24:56 -07:00
tangxifan 9e60f62299 [Testbench] Critical bug fix on the caravel testbench for and2_latch benchmark 2020-12-18 16:23:50 -07:00
tangxifan 7b2632a872 [Testbench] Add power pin support to scff testbench 2020-12-18 15:55:05 -07:00
tangxifan 2b0294e40a [Testbench] Recover from LFS 2020-12-18 15:39:00 -07:00
tangxifan f258cefd9a [QLSOFA-HD] Patch on lvs netlist 2020-12-18 10:55:17 -07:00
tangxifan 7ea8f77038 [Testbench] Add include netlist for caravel testbench 2020-12-17 20:20:39 -07:00
tangxifan 187364ebc3 [Testbench] Add Caravel testbench for and2_testbench 2020-12-17 20:19:12 -07:00
tangxifan 5da9696e63
Merge pull request #74 from lnis-uofu/xt_dev 
Testbenches for Caravel + FPGA integration
 2020-12-17 16:25:37 -07:00
tangxifan 2a429178c7
Merge pull request #75 from lnis-uofu/ganesh_dev 
General updates to pass MPW precheker
 2020-12-17 16:24:43 -07:00
Ganesh Gore fa0ae58192 [Actions] Removed HD action 2020-12-17 15:29:18 -07:00
Ganesh Gore 85a59e4673 [CI] Precheck related updates 2020-12-17 15:01:49 -07:00
tangxifan d6b435018c [Testbench] Rename top modules of Caravel testbenches to be compatible with scripted verification flow 2020-12-17 10:45:33 -07:00
tangxifan 46bd96f8e9 [Testbench] Add carevel testbench for ccff test 2020-12-17 10:45:06 -07:00
tangxifan d019166190 [Testbench] Bug fix in Caravel ccff testbench 2020-12-17 10:36:25 -07:00
Ganesh Gore 37bca4684b [BugFix] After Integration with mpw-one-b 2020-12-17 09:29:54 -07:00
Tarachand Pagarani 8d5036f108 commented/corrected failing benchmarks 2020-12-17 05:46:30 -08:00