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simulation_info_writer.cpp
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start bring back ini writer bit by bit
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2019-11-02 18:20:25 -06:00 |
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simulation_info_writer.h
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remove unused variable in sim info writer
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2019-11-02 16:35:32 -06:00 |
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verilog_api.c
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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verilog_api.h
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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verilog_autocheck_top_testbench.c
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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verilog_autocheck_top_testbench.h
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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verilog_compact_netlist.c
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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verilog_compact_netlist.h
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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verilog_decoder.c
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fix
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2019-10-01 16:54:16 -06:00 |
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verilog_decoder.h
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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verilog_decoders.cpp
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pass current regression tests
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2019-10-30 19:10:36 -06:00 |
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verilog_decoders.h
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start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
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verilog_essential_gates.cpp
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add const 0 and 1 module Verilog generation
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2019-10-21 14:17:09 -06:00 |
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verilog_essential_gates.h
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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verilog_formal_random_top_testbench.cpp
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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verilog_formal_random_top_testbench.h
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remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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verilog_formality_autodeck.c
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bring ini writer for formality scripts back
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2019-11-02 18:56:54 -06:00 |
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verilog_formality_autodeck.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_global.c
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Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
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verilog_global.h
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reworked the ini writer
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2019-11-01 20:25:01 -06:00 |
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verilog_grid.cpp
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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verilog_grid.h
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add grid module generation
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2019-10-22 16:14:11 -06:00 |
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verilog_include_netlists.c
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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verilog_include_netlists.cpp
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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verilog_include_netlists.h
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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verilog_lut.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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verilog_lut.h
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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verilog_memory.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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verilog_memory.h
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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verilog_modelsim_autodeck.c
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_modelsim_autodeck.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_module_writer.cpp
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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verilog_module_writer.h
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developing verilog writer for generic module graph
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2019-10-10 20:09:55 -06:00 |
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verilog_mux.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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verilog_mux.h
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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verilog_pbtypes.c
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refactored port addition for pb_types in Verilog generation
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2019-10-08 14:03:17 -06:00 |
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verilog_pbtypes.h
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Latest version, not stable yet but close
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2019-07-09 08:34:01 -06:00 |
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verilog_preconfig_top_module.cpp
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fine tuning top testbench and getting ready for testing
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2019-11-04 12:08:36 -07:00 |
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verilog_preconfig_top_module.h
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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verilog_primitives.c
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Fully functional
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2019-09-13 16:02:06 -06:00 |
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verilog_primitives.h
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Include new files in the parameter spreading
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2019-07-01 11:27:48 -06:00 |
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verilog_report_timing.c
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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verilog_report_timing.h
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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verilog_routing.c
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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verilog_routing.h
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refactored routing module generation and verilog writing
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2019-10-23 11:46:55 -06:00 |
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verilog_sdc.c
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-09-13 16:02:06 -06:00 |
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verilog_sdc.h
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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verilog_sdc_pb_types.c
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Break memories even in the clb sdc
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2019-06-16 14:27:29 -06:00 |
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verilog_sdc_pb_types.h
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clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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verilog_submodule_utils.cpp
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minor tuning on the delay assignment
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2019-08-21 23:11:54 -06:00 |
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verilog_submodule_utils.h
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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verilog_submodules.c
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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verilog_submodules.h
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-25 15:33:37 -06:00 |
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verilog_tcl_utils.c
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-09-13 16:02:06 -06:00 |
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verilog_tcl_utils.h
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Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
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verilog_testbench_utils.cpp
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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verilog_testbench_utils.h
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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verilog_top_module.cpp
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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verilog_top_module.h
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add top module generation and refactored verilog generation for top module
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2019-10-23 12:16:58 -06:00 |
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verilog_top_netlist_utils.c
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Explicit verilog passing all tests
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2019-10-02 10:22:28 -06:00 |
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verilog_top_netlist_utils.h
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Latest version explicit
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2019-07-11 14:33:56 -06:00 |
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verilog_top_testbench.c
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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verilog_top_testbench.cpp
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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verilog_top_testbench.h
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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verilog_utils.c
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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verilog_utils.h
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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verilog_verification_top_netlist.c
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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verilog_verification_top_netlist.h
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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verilog_wire.cpp
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add wire module generation and simplify Verilog generation for wires
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2019-10-21 20:20:34 -06:00 |
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verilog_wire.h
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refactored wire Verilog generation
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2019-09-12 20:49:02 -06:00 |
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verilog_writer_utils.cpp
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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verilog_writer_utils.h
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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