146 lines
7.0 KiB
C
146 lines
7.0 KiB
C
/***********************************/
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/* Synthesizable Verilog Dumping */
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/* Xifan TANG, EPFL/LSI */
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/***********************************/
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#include <stdio.h>
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#include "spice_types.h"
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#include "linkedlist.h"
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#include "fpga_x2p_globals.h"
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#include "verilog_global.h"
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char* verilog_netlist_file_postfix = ".v";
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float verilog_sim_timescale = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
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char* verilog_timing_preproc_flag = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
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char* verilog_signal_init_preproc_flag = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation
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char* verilog_formal_verification_preproc_flag = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
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char* initial_simulation_flag = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
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char* autochecked_simulation_flag = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
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char* formal_simulation_flag = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
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char* default_verilog_dir_name = "syn_verilogs/";
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char* default_src_dir_name = "SRC/";
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char* default_lb_dir_name = "lb/";
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char* default_rr_dir_name = "routing/";
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char* default_submodule_dir_name = "sub_module/";
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char* default_tcl_dir_name = "SCRIPTS/";
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char* default_sdc_dir_name = "SDC/";
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char* default_msim_dir_name = "MSIM/";
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char* default_snpsfm_dir_name = "SNPS_FM/";
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char* default_modelsim_dir_name = "msim_projects/";
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char* default_report_timing_rpt_dir_name = "RPT/";
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char* autocheck_testbench_postfix = "_autocheck";
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char* modelsim_project_name_postfix = "_fpga_msim";
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char* modelsim_proc_script_name_postfix = "_proc.tcl";
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char* modelsim_top_script_name_postfix = "_runsim.tcl";
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char* modelsim_testbench_module_postfix = "_top_tb";
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char* modelsim_autocheck_testbench_module_postfix = "_autocheck_top_tb";
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char* modelsim_simulation_time_unit = "ms";
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char* formal_verification_top_module_postfix = "_top_formal_verification";
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char* formal_verification_top_module_port_postfix = "_fm";
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char* formal_verification_top_module_uut_name = "U0_formal_verification";
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// Formality script generation variables
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char* formality_script_name_postfix = "_formality_script.tcl";
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char* formal_verification_top_postfix = "_top_formal_verification";
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// End of Formality script generation variables
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// Icarus variables and flag
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char* icarus_simulator_flag = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
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// End of Icarus variables and flag
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char* verilog_top_postfix = "_top.v";
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char* formal_verification_verilog_file_postfix = "_top_formal_verification.v";
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char* top_testbench_verilog_file_postfix = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */
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char* autocheck_top_testbench_verilog_file_postfix = "_autocheck_top_tb.v"; /* !!! must be consist with the modelsim_autocheck_testbench_module_postfix */
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char* random_top_testbench_verilog_file_postfix = "_formal_random_top_tb.v";
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char* blif_testbench_verilog_file_postfix = "_blif_tb.v";
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char* defines_verilog_file_name = "fpga_defines.v";
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char* defines_verilog_simulation_file_name = "define_simulation.v";
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char* submodule_verilog_file_name = "sub_module.v";
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char* logic_block_verilog_file_name = "logic_blocks.v";
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char* luts_verilog_file_name = "luts.v";
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char* routing_verilog_file_name = "routing.v";
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char* muxes_verilog_file_name = "muxes.v";
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char* local_encoder_verilog_file_name = "local_encoder.v";
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char* memories_verilog_file_name = "memories.v";
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char* wires_verilog_file_name = "wires.v";
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char* essentials_verilog_file_name = "inv_buf_passgate.v";
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char* config_peripheral_verilog_file_name = "config_peripherals.v";
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char* user_defined_template_verilog_file_name = "user_defined_templates.v";
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/* File names for Report Timing */
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char* trpt_sb_file_name = "report_timing_sb.tcl";
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char* trpt_routing_file_name = "report_timing_routing.tcl";
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/* File names for SDC*/
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char* sdc_analysis_file_name = "fpga_top_analysis.sdc";
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char* sdc_break_loop_file_name = "break_loop.sdc";
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char* sdc_constrain_routing_chan_file_name = "routing_channels.sdc";
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char* sdc_constrain_cb_file_name = "cb.sdc";
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char* sdc_constrain_sb_file_name = "sb.sdc";
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char* sdc_clock_period_file_name = "clb_clock.sdc";
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char* sdc_constrain_pb_type_file_name = "clb_constraints.sdc";
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char* sdc_break_vertical_sbs_file_name = "break_horizontal_sbs.sdc"; /* We break the vertical to read the horizontal */
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char* sdc_break_horizontal_sbs_file_name = "break_vertical_sbs.sdc"; /* We break the horizontal to read the vertical */
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char* sdc_restore_vertical_sbs_file_name = "restore_horizontal_sbs.sdc"; /* We break the vertical to read the horizontal */
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char* sdc_restore_horizontal_sbs_file_name = "restore_vertical_sbs.sdc"; /* We break the horizontal to read the vertical */
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char* verilog_mux_basis_posfix = "_basis";
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char* verilog_mux_special_basis_posfix = "_special_basis";
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char* verilog_mem_posfix = "_mem";
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char* verilog_config_peripheral_prefix = "config_peripheral";
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/* Prefix for subckt Verilog netlists */
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char* grid_verilog_file_name_prefix = "grid_";
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char* chanx_verilog_file_name_prefix = "chanx_";
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char* chany_verilog_file_name_prefix = "chany_";
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char* sb_verilog_file_name_prefix = "sb_";
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char* cbx_verilog_file_name_prefix = "cbx_";
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char* cby_verilog_file_name_prefix = "cby_";
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/* SRAM SPICE MODEL should be set as global*/
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t_spice_model* sram_verilog_model = NULL;
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/* Input and Output Pad spice model. should be set as global */
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t_spice_model* iopad_verilog_model = NULL;
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/* Linked-list that stores all the configuration bits */
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t_llist* conf_bits_head = NULL;
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/* Linked-list that stores submodule Verilog file mames */
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t_llist* grid_verilog_subckt_file_path_head = NULL;
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t_llist* routing_verilog_subckt_file_path_head = NULL;
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t_llist* submodule_verilog_subckt_file_path_head = NULL;
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int verilog_default_signal_init_value = 0;
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char* top_netlist_bl_enable_port_name = "en_bl";
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char* top_netlist_wl_enable_port_name = "en_wl";
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char* top_netlist_bl_data_in_port_name = "data_in";
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char* top_netlist_addr_bl_port_name = "addr_bl";
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char* top_netlist_addr_wl_port_name = "addr_wl";
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char* top_netlist_array_bl_port_name = "bl_bus";
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char* top_netlist_array_wl_port_name = "wl_bus";
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char* top_netlist_array_blb_port_name = "blb_bus";
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char* top_netlist_array_wlb_port_name = "wlb_bus";
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char* top_netlist_reserved_bl_port_postfix = "_reserved_bl";
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char* top_netlist_reserved_wl_port_postfix = "_reserved_wl";
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char* top_netlist_normal_bl_port_postfix = "_bl";
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char* top_netlist_normal_wl_port_postfix = "_wl";
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char* top_netlist_normal_blb_port_postfix = "_blb";
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char* top_netlist_normal_wlb_port_postfix = "_wlb";
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char* top_netlist_scan_chain_head_prefix = "cc_in";
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char* top_tb_reset_port_name = "greset";
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char* top_tb_set_port_name = "gset";
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char* top_tb_prog_reset_port_name = "prog_reset";
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char* top_tb_prog_set_port_name = "prog_set";
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char* top_tb_config_done_port_name = "config_done";
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char* top_tb_op_clock_port_name = "op_clock";
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char* top_tb_prog_clock_port_name = "prog_clock";
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char* top_tb_inout_reg_postfix = "_reg";
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char* top_tb_clock_reg_postfix = "_reg";
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