tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
|
a8c803f08f
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try to fix bugs in explicit port mapping
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2019-09-02 16:37:43 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
|
27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
|
ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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tangxifan
|
39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
|
fcb31e4c24
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add stats for verilog modules
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2019-08-23 18:41:16 -06:00 |
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tangxifan
|
8eebca9daa
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plug in module manager
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2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
37a092e885
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add recursive global port searching for circuit library
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2019-08-23 16:36:30 -06:00 |
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tangxifan
|
931b042750
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refactoring module manager
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2019-08-23 12:52:01 -06:00 |
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tangxifan
|
732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |
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tangxifan
|
d8eb9866a0
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refactored gate verilog generation
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2019-08-21 18:49:48 -06:00 |
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tangxifan
|
5f55fc7b49
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add missing files and developing essential gates
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2019-08-20 20:43:46 -06:00 |
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tangxifan
|
60e8d2b29f
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add missing files and try to refactor submodule essential
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2019-08-20 16:13:08 -06:00 |
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tangxifan
|
29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
a7ac1e4980
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remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
5ece7ab6d0
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start refactoring the bitstream part using spice_models
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2019-08-16 15:58:14 -06:00 |
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tangxifan
|
4eb046760b
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still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
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2019-08-15 21:57:59 -06:00 |
|
tangxifan
|
d2d8af5416
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bug fixing for pb_type num_conf_bits and num_iopads stats
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2019-08-13 17:34:09 -06:00 |
|
tangxifan
|
edfa72a666
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try to fix the bug in clock net identification
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2019-08-13 16:47:28 -06:00 |
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tangxifan
|
392f579836
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add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
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tangxifan
|
c004699a14
|
complete parsers for ports
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2019-08-09 21:00:41 -06:00 |
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tangxifan
|
74da4ed51a
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start creating the class for circuit models
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2019-08-07 11:38:45 -06:00 |
|
tangxifan
|
b4f3dfc82d
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bug fixing for local encoder's bitstream generation
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2019-08-06 14:17:57 -06:00 |
|
tangxifan
|
890ff05628
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bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
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2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
bcc6346533
|
speeding up identifying unique modules in routing
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2019-07-14 13:49:20 -06:00 |
|
tangxifan
|
4c6e245885
|
speed-up the unique routing process
|
2019-07-14 12:22:00 -06:00 |
|
tangxifan
|
b690e702f6
|
adding more info to show the progress bar in backannotating GSBs
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2019-07-13 19:53:44 -06:00 |
|
tangxifan
|
aa4cd850ae
|
try to optimize the runtime of routing uniqueness detection
|
2019-07-13 18:10:34 -06:00 |
|
tangxifan
|
78578f66c5
|
bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
|
2019-07-13 14:48:32 -06:00 |
|
tangxifan
|
f0ecc51b51
|
bug fixing to resolve the conflicts between explicit port map and standard cell map
|
2019-07-12 10:38:20 -06:00 |
|
tangxifan
|
acee0161c7
|
Merge branch 'tileable_routing' into dev
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2019-07-10 15:13:24 -06:00 |
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tangxifan
|
b7f9831bd2
|
add statistics for unique GSBs
|
2019-07-10 13:08:03 -06:00 |
|
tangxifan
|
c6a4d29ed8
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 12:05:43 -06:00 |
|
tangxifan
|
edfe3144c3
|
update profiling, found where runtime is lost
|
2019-07-09 20:28:01 -06:00 |
|
tangxifan
|
737cc2874f
|
Merge branch 'tileable_routing' into dev
|
2019-07-09 17:42:44 -06:00 |
|
tangxifan
|
65f696c1d7
|
fix critical bugs in rectangle floorplan
|
2019-07-09 17:41:20 -06:00 |
Baudouin Chauviere
|
4ca0967453
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-09 14:35:51 -06:00 |
|
tangxifan
|
5d5e09fcdb
|
minor fix in trying to accelerate the unique routing functions
|
2019-07-08 17:12:36 -06:00 |
|
tangxifan
|
d64aeef5c4
|
add profiling to routing compact process
|
2019-07-03 16:57:34 -06:00 |
|
tangxifan
|
1a1da30ae9
|
fixed a critical bug in using tileable route chan W
|
2019-07-03 16:46:43 -06:00 |
|
tangxifan
|
b79d276ea9
|
add profiling to fpga_x2p_setup
|
2019-07-03 14:44:54 -06:00 |
|
tangxifan
|
02398818a9
|
update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
|
2019-07-03 10:33:02 -06:00 |
|
tangxifan
|
95674c4687
|
added Switch Block SubType and SubFs for tileable rr_graph generation
|
2019-07-02 10:00:02 -06:00 |
|
Baudouin Chauviere
|
0e04b88c8f
|
Include new files in the parameter spreading
|
2019-07-01 11:27:48 -06:00 |