Commit Graph

89 Commits

Author SHA1 Message Date
tangxifan 0b6a9b06f5 [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality 2021-07-02 10:39:07 -06:00
ANDREW HARRIS POND 1d281765ea fixed tab spacing 2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND 808821bb8c fixed errors 2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench 2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND 2567fbee05 ready to merge 2021-07-01 15:28:59 -06:00
tangxifan 04ceeefb0a
Merge branch 'master' into verilog_testbench 2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND db9231c225 tests failing with initial blocks 2021-07-01 13:52:28 -06:00
Andrew Pond fab2b069f0 added signal gen regression test to shell script 2021-06-30 16:18:09 -06:00
tangxifan a898537474 [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` 2021-06-30 15:29:13 -06:00
tangxifan 4d4577bb83 [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders 2021-06-30 15:13:47 -06:00
tangxifan 477cba1c7e
Merge branch 'master' into verilog_testbench 2021-06-23 09:18:18 -06:00
tangxifan 0a0d10b36d [HDL] Bug fix in Verilog syntax 2021-06-22 16:18:46 -06:00
tangxifan 07dcf3ad27 [HDL] Add more micro benchmarks for counter, and-gate and mac unit 2021-06-21 16:48:35 -06:00
Andrew Pond 3cfc42cdf9 added testbench CI 2021-06-15 14:16:31 -06:00
Andrew Pond 12b44e0eca added configuration benchmark files 2021-05-13 10:04:23 -06:00
tangxifan 16fff90607 [Benchmark] Add microbenchmark 1-bit blinking 2021-05-06 15:17:27 -06:00
tangxifan a571b063b6 [Benchmark] Add 1k DPRAM benchmark which can fit new arch 2021-04-28 11:26:31 -06:00
tangxifan 7d059f7407 [Benchmark] Bug fix in dual port ram 16k benchmark 2021-04-27 23:33:20 -06:00
tangxifan 3c1c33bf1e [Benchmark] Add a microbenchmark just fit 16k dual port ram 2021-04-27 22:51:43 -06:00
tangxifan 7e2368158e [Benchmark] move benchmarks to microbenchmark category 2021-04-27 22:12:30 -06:00
tangxifan 5a85ec9fa0 [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00
tangxifan 1d498bb296 [Benchmark] Add a scalable micro benchmark fifo 2021-04-27 15:26:52 -06:00
tangxifan 200b6d39a6 [Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit 2021-04-23 20:36:28 -06:00
tangxifan 671394ec2c [Benchmark] Add microbenchmarks for mac with different sizes for DSP testing 2021-04-23 20:33:43 -06:00
tangxifan b203ef7bc2 [Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs 2021-04-21 14:03:51 -06:00
tangxifan c020333512
Merge branch 'master' into dff_techmap 2021-04-16 20:54:28 -06:00
tangxifan bbdc0e53af [Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures 2021-04-16 20:14:48 -06:00
tangxifan e46c6e75a3 [Benchmark] Add missing RTL for IWLS2005 benchmarks 2021-04-16 16:50:41 -06:00
tangxifan 26d3b5a954 [Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches 2021-04-16 16:08:58 -06:00
tangxifan 86ad572530 [Benchmark] Add opencore RTLs from IWLS 2005 benchmarks 2021-04-16 14:27:54 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan be03eafd66 [Benchmark] Add a micro benchmark: 8-bit multiply and accumulate 2021-03-23 15:33:37 -06:00
tangxifan 55d1004cf2 [Benchmark] Add missing DPRAM module to LU32PEEng 2021-03-22 14:41:38 -06:00
tangxifan 5fc83ebea3 [Benchmark] Add missing DPRAM modules to LU8PEEng 2021-03-22 14:38:00 -06:00
tangxifan b828f91a78 [Benchmark] Add missing DPRAM and SPRAM modules to mcml 2021-03-22 14:13:05 -06:00
tangxifan b906ab814e [Benchmark] Add missing DPRAM module to mkPktMerge 2021-03-22 12:51:23 -06:00
tangxifan 310c2a9495 [Benchmark] Add missing DPRAM module to mkDelayWorker32B 2021-03-22 12:51:02 -06:00
tangxifan 707247283c [Benchmark] Add missing DPRAM module to mkSMAdapter4B 2021-03-22 12:50:39 -06:00
tangxifan eb056e2afd [Benchmark] Add missing DPRAM module to or1200 2021-03-22 12:50:17 -06:00
tangxifan 169ee53b79 [Benchmark] Add missing modules to VTR benchmarks 2021-03-20 22:53:17 -06:00
tangxifan 2bd8ef2af9 [Benchmark] Patch boundtop.v with missing SPRAM module 2021-03-20 21:00:53 -06:00
tangxifan 6bf4880c50 [benchmark] Add vtr benchmark 2021-03-17 15:24:26 -06:00
Tarachand Pagarani ce76c58422 add shift register test case 2021-03-05 09:06:05 -08:00
tangxifan 2dbdc2644f [Benchmark] Remove replicate micro benchmarks 2021-02-22 10:22:19 -07:00
Lalit Narain Sharma be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
Lalit Sharma 576e6753f6 Removing 2 more tests which are variant of and design 2021-02-19 09:11:19 -08:00
Lalit Sharma d4c5a5655a Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
tangxifan 1f097abe99 [Benchmark] Add micro benchmark for FIR filter 2021-02-18 19:37:44 -07:00
Lalit Sharma 44a979288b Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
tangxifan 1712ee4edb [Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture 2021-02-09 15:41:21 -07:00