victorzh001
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04a60ca4b5
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Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-10 11:01:47 +08:00 |
Victor
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3ea830e168
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Add the reference_file to the index.rst
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2024-09-10 10:46:15 +08:00 |
tangxifan
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7250a7d703
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[core] code format
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2024-09-09 12:46:46 -07:00 |
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tangxifan
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e3b99e88ff
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[core] syntax
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2024-09-09 12:46:23 -07:00 |
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tangxifan
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fc92ecea24
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[core] typo
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2024-09-09 12:43:38 -07:00 |
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tangxifan
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5f50e4623c
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[core] add a new option map_global_net_to_msb for pb_pin_fixup
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2024-09-09 12:21:09 -07:00 |
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tangxifan
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37cac3d679
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Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-08 21:13:48 -07:00 |
rafljiarui
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f7aaead513
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Fixed typo in vpr-main.cpp
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2024-09-06 13:14:59 -05:00 |
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Victor
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9a2fc86dcd
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add dependency on build_fabric
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2024-09-06 17:58:47 +08:00 |
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Victor
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7bacc781d0
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update code according to code review comments
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2024-09-06 15:39:08 +08:00 |
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Victor
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4aca4fda6f
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fix issue in reg test
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2024-09-05 10:43:53 +08:00 |
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Victor
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ba5c8a3364
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update code format
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2024-09-03 11:20:51 +08:00 |
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Victor
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0093d4b269
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Add command report_reference
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2024-09-02 15:21:50 +08:00 |
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tangxifan
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4b54e6fad1
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[core] fixed a corner case where spine usage should be updated after each switch point connection
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2024-08-15 20:12:31 -07:00 |
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tangxifan
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642cb6eb9a
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[core] coord adjustment should occur based on des coord
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2024-08-15 14:28:29 -07:00 |
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tangxifan
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c7da894eaf
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[core] fixed a bug where some spine was wrongly disabled
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2024-08-15 14:10:34 -07:00 |
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tangxifan
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5877a3f7be
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[core] code format
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2024-08-15 12:44:03 -07:00 |
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tangxifan
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00fd21704c
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[core] fixed a bug where the switch point coordinate of src spine required adjustment
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2024-08-15 12:41:09 -07:00 |
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tangxifan
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1bcb0d0868
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[core] code format
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2024-08-14 18:09:44 -07:00 |
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tangxifan
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4554c5781a
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[core] fixed a bug where some clock spine was wrongly marked unused
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2024-08-14 18:08:01 -07:00 |
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tangxifan
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fc06aacc4e
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[core] code format
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2024-08-14 10:49:36 -07:00 |
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tangxifan
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665777df51
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[core] fixed some bug
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2024-08-14 10:49:12 -07:00 |
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tangxifan
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76e03e3e14
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[core] code format
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2024-08-13 23:25:04 -07:00 |
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tangxifan
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735adab9df
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[core] syntax due to clang
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2024-08-13 23:24:28 -07:00 |
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tangxifan
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eb7639f44b
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[core] code format
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2024-08-13 22:37:34 -07:00 |
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tangxifan
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812686d169
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[core] support global net fixup in pb pin fixup
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2024-08-13 22:36:37 -07:00 |
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tangxifan
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ba5994a14c
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[core] more debugging messages
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2024-08-13 21:03:49 -07:00 |
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tangxifan
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c2d9696489
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[core] fixed a bug where some spines are not disabled
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2024-08-13 15:19:47 -07:00 |
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tangxifan
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ad13058a0b
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[core] fixed a bug where unused last-level of clock spines are not disabled
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2024-08-13 15:04:13 -07:00 |
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tangxifan
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4def678b11
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[core] code format
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2024-08-09 18:20:18 -07:00 |
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tangxifan
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1af1306444
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[core] fixed a bug where pin index for subtile is wrongly calculated for clock network taps
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2024-08-09 18:02:49 -07:00 |
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tangxifan
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f1ab44a212
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[core] fixed a bug
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2024-08-09 17:10:58 -07:00 |
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tangxifan
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e4d7192e50
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[core] fixed a bug where subtile was used for clock network tap name
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2024-08-09 16:16:05 -07:00 |
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tangxifan
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1d5acea7e0
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[core] typo
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2024-08-06 20:17:15 -07:00 |
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tangxifan
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1225679aac
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[core] code format
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2024-08-06 17:35:44 -07:00 |
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tangxifan
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0dba4082d1
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[core] syntax
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2024-08-06 17:20:34 -07:00 |
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tangxifan
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ac2337d24b
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[core] rework the option 'constant_undriven_inputs'
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2024-08-06 16:50:49 -07:00 |
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tangxifan
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2e6b311d04
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[core] add more details to debug messages
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2024-08-02 18:33:43 -07:00 |
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tangxifan
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eeaa3373c6
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[core] code format
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2024-08-02 17:48:47 -07:00 |
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tangxifan
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82cf7bbb8c
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[core] Add verbose mode on find_node() for clock rr graph
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2024-08-02 17:47:41 -07:00 |
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tangxifan
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1ec5847d5a
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[core] typo
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2024-08-02 14:27:43 -07:00 |
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tangxifan
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f44c45bdd3
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[core] code format
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2024-08-02 14:23:35 -07:00 |
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tangxifan
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f7e30b9974
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[core] fixed a bug where pb pin fixup does not support perimeter cb
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2024-08-02 14:21:22 -07:00 |
chungshien
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b3c8c529d5
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Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
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2024-07-31 12:25:37 -07:00 |
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tangxifan
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d6db51f29e
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[core] code format
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2024-07-30 19:09:31 -07:00 |
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tangxifan
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ef6b6f8e40
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[core] remove warnings
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2024-07-30 18:50:49 -07:00 |
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tangxifan
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ae95357991
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[core] code format
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2024-07-30 15:40:41 -07:00 |
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tangxifan
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a2c3af60d7
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[core] fixed a bug where unique cb module is not considered as entry point
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2024-07-30 15:39:44 -07:00 |
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tangxifan
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853883cd36
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[core] code format
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2024-07-30 12:56:03 -07:00 |
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tangxifan
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234eee19ae
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[core] revert
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2024-07-30 12:29:32 -07:00 |