tangxifan
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933801cfa7
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update documentation about alias support in fabric key
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2020-06-27 15:04:04 -06:00 |
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tangxifan
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db5397fa75
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update tutorial about architecture to synchronize with latest file organization
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2020-06-24 10:51:26 -06:00 |
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tangxifan
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161d1474c1
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keep tutorial updated to the latest regression test organization
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2020-06-24 10:36:08 -06:00 |
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tangxifan
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8b8d92d186
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update documentation for new bitstream file format
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2020-06-20 18:59:45 -06:00 |
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tangxifan
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91b072d7c5
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documentation update on the bitstream file format to synchronize with the latest codes
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2020-06-17 11:56:40 -06:00 |
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tangxifan
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ba38120093
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add documentation for fabric key and reorganize command references
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2020-06-12 16:15:16 -06:00 |
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tangxifan
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1a006f2ddb
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update documentation for separated XML files
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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b9dd47d465
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update documentation about memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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c00653961e
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minor format fix in documentation
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0931eccbf6
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update documentation for the fast configuration options
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fe2ba7d50a
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update documentation for standalone configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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de07712a3a
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update documentation about the frame-based configuration protocol
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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1150b903a5
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add quick start tutorial for architecture modeling
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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339bf87c43
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add missing file
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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aa77ee9af6
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add tutorial for full testbench run
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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35536ee594
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renaming design flows in documentation
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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011ce5cdf6
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minor fix on the documentation
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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f079c61bd3
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re organize tutorials
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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dcce782a46
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update documentation about Verilog testbenches
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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c5a3e44e61
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Update Verilog fabric netlist documentation
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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cae7fe0fed
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minor fix on the manual subtree
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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c27d77a418
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |
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tangxifan
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f6895fcc14
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update documentation for new options of Verilog testbench writer
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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c2a81c76e1
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update doc for new options
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
f4dd882f0f
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documentation updated for new command
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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df9cf32b49
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update documenation for configuration chain writer
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2020-06-11 19:31:06 -06:00 |
|
Xifan Tang
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24934aff86
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update documentation on the depth option for fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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Xifan Tang
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752470c2da
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update documentation on write hierarchy command and options
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2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
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ac378febef
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update doc about time units in SDC generator
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2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
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d18e924a89
|
Update documentation on new fpga_sdc option
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2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
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ecdbdcb592
|
update documentation on new SDC options
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2020-06-11 19:31:02 -06:00 |
|
Xifan Tang
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52adebacfb
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update doc for file options in openfpga bitstream
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2020-04-21 14:40:53 -06:00 |
|
Xifan Tang
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b4542ea34b
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minor fix on doc about the global and general purpose port
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2020-04-09 17:10:04 -06:00 |
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Xifan Tang
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d99776b260
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update documentation on the global I/O ports
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2020-04-08 18:18:53 -06:00 |
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Xifan Tang
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b9ade3fcb6
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documentation update to introduce new features in script mode of OpenFPGA shell
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2020-04-08 14:13:28 -06:00 |
|
Xifan Tang
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55e68896d6
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doc update for the support on std cell MUX2 and examples
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2020-04-07 12:01:13 -06:00 |
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Xifan Tang
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7a4137fdcf
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doc update for packable XML syntax in VPR
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2020-04-06 18:37:05 -06:00 |
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Xifan Tang
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1a3a748dd2
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update documentation with the support on spypads and global I/O ports
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2020-04-05 20:12:28 -06:00 |
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Xifan Tang
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6ce0fe4ef2
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doc update for FPGA-bitstream to better motivate the different types of bitstream
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2020-04-01 12:57:28 -06:00 |
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Xifan Tang
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fd8248d9dd
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update documentation: the addon syntax on VPR and configuration protocols
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2020-04-01 12:35:52 -06:00 |
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tangxifan
|
78964ce71c
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update documentation on the through channel
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2020-03-27 11:34:39 -06:00 |
|
Xifan Tang
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b4221e94bb
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add documentation on the tileable routing and thru channel support
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2020-03-25 16:52:42 -06:00 |
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Xifan Tang
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cb6afea07c
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update documentation on a new option in FPGA-SDC to constrain zero-delay paths
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2020-03-25 16:00:25 -06:00 |
|
Xifan Tang
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3a74fb7a04
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update documentation for the new options
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2020-03-25 15:23:21 -06:00 |
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Xifan Tang
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7e3a8e5794
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typo fixed in fpga-bitstream documentation
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2020-03-22 16:27:12 -06:00 |
|
Xifan Tang
|
75dfe6a045
|
update documentation for write_gsb_to_xml functionality
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2020-03-22 16:21:35 -06:00 |
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tangxifan
|
1d766d2a70
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minor format fix on documentation
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2020-03-11 10:22:30 -06:00 |
|
Xifan Tang
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b941ac8a4a
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remove deprecated options
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2020-03-10 20:58:00 -06:00 |
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Xifan Tang
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8037d1ad93
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-03-10 20:55:02 -06:00 |
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Xifan Tang
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9f743f7f4e
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add openfpga shell documentation
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2020-03-10 20:54:42 -06:00 |