3b6cd885f3
BugFix: Fixed yosys_vpr with openFPGA_Shell
2020-07-22 11:57:04 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
41585436c8
Added external_fabric_key_file key
2020-06-12 15:37:12 -06:00
c1b73efa62
Added support for simulation setting file in the task flow
2020-06-10 23:12:30 -06:00
a3103f6afe
BugFix : Relative path for refrence benchmark fixed
2020-04-25 20:16:17 -06:00
9d1b3d6865
Fixed modelsim include references
2020-04-24 21:53:57 -06:00
689c4a3e19
BugFix: The filename in the previous commit
2020-04-15 12:44:22 -06:00
7f37bf1441
Added formal verification support to fpga_flow script
2020-04-15 12:24:51 -06:00
f6b3c5854a
Bugfix :
...
+ OpenFPGA template variables update
+ Default path for the verilog netlist
2020-04-11 16:45:22 -06:00
8ea272dc2c
Patched the OpenFPGA shell execution bug
2020-04-08 21:28:14 -06:00
583a4d8767
Fixed bug in openfpga_flow script
2020-04-08 12:04:08 -06:00
ea4122a8a4
Updated openfpga_flow and task file to support sheel run
2020-04-06 00:34:36 -06:00
d1d3446568
backedup partial upgrade for fpga_flow script
2020-04-05 11:36:24 -06:00
46bb5ef9d0
Added disp option in openfpga_flow, Default is --nodisp
2020-01-23 10:04:38 -07:00
f0bed1244c
Added blif file folding before VPR run
2020-01-09 16:50:34 -07:00
74b650e9e1
Added fpga_x2p_duplicate_grid_pin option
2019-12-30 12:25:28 -07:00
d1e260f54f
Spice related option added
2019-12-30 12:16:04 -07:00
6bb11918dc
Updated modelsim and collected result
2019-11-16 19:10:04 -07:00
00ec36c1af
Added Modelsim error check in log
2019-11-16 13:18:13 -07:00
373dbe0718
First draft for multithreaded Modelsim simulation
2019-11-16 01:06:09 -07:00
f05aede868
Added task support for modelsim script
2019-11-15 23:23:15 -07:00
f52eaef622
Updated flow script and skipped travis upload on failure test setup.
2019-11-15 14:35:15 -07:00
4df6402241
add python script for batch simulations
2019-11-15 14:23:03 -07:00
a880802803
Bug Fix: Corrected read VPR stat filename
2019-11-01 20:51:05 -06:00
595d2d3070
Simple argument shuffle
2019-11-01 18:21:26 -06:00
27005d6640
Added Modelsim Python Script
2019-11-01 18:20:40 -06:00
81180939ca
Bug fix: Missing exit_if_fail flag in fpga_flow script
2019-10-31 09:56:57 -06:00
c034b871bb
Made activity file independent of power option
2019-10-15 16:08:25 -06:00
eaf8ecee86
added _vpr.txt subscript to vpr log files
2019-10-15 16:07:34 -06:00
d269472daf
Updated formality python script
2019-09-27 14:00:57 -06:00
50039a4b6e
Added remove run directory option
2019-09-21 23:35:56 -06:00
cd5fd6ce6c
Added explicit checking to VVP execution
2019-09-18 12:14:26 -06:00
169732ccc1
Added verbose option in VVP output
2019-09-17 22:09:37 -06:00
678e3181ba
Made compact_routing_hierarchy options uncond
2019-09-16 21:22:13 -06:00
81b9c5b266
Added flag for VVP exit code
2019-09-14 12:35:47 -06:00
e5c99c8b12
Quick terminate on fail added
2019-09-13 23:56:38 -06:00
bd9e57bc37
Added better task name
2019-09-13 23:30:42 -06:00
a6e592247e
Replaced options exit_on fail and show_thread logs
2019-09-13 22:50:20 -06:00
d64bb18346
Separated Modelsim tcl script generation
2019-09-07 12:36:22 -04:00
bcbcd463fe
Added pending runs in log
2019-09-06 11:48:13 -04:00
702a7683a8
Ensure strict exit of fpga_flow on error
2019-09-05 10:23:35 -06:00
48ec1eefcd
Added fpga_task cmd options in doc [ci skip]
2019-09-02 02:45:05 -06:00
241b001282
Added openfpga_task doc
2019-09-01 22:15:53 -06:00
ad4c688206
Added print for JobID to architecture mapping
2019-08-31 22:04:57 -06:00
f4e99c150a
resolve missing variable bug
2019-08-31 21:55:32 -06:00
3d4f7f66fd
Updated to run with python3
2019-08-31 21:42:31 -06:00
06c0dbb328
Added docuementation for fpga_flow
2019-08-31 15:19:34 -06:00
02137805c7
Added python version check in flow and task scripts
2019-08-29 22:14:30 -06:00
a25124b58c
Added additional PATH variables
2019-08-29 21:37:07 -06:00
f54a8522fa
Log prints task stats
2019-08-27 22:04:32 -06:00
715adc13ff
Failed result do not throw error
2019-08-27 21:25:38 -06:00
632c9d6976
Added python execution path in config file
2019-08-25 00:42:48 -06:00
f558437ae1
Added task for vpr_blif flow
2019-08-25 00:23:39 -06:00
6e7de16ad4
Solved bug in commnad rearrangement
2019-08-22 23:41:25 -06:00
77e2a7bca3
Added execution time logs in flow script
2019-08-22 17:01:38 -06:00
30cbe38d3d
Added Test Modes - Added blif VPR Option
2019-08-22 17:00:59 -06:00
d5ce1b557e
Made thread logs prettier
2019-08-22 16:56:58 -06:00
764d7039b5
Import utils bug fixing for travis test
2019-08-21 12:42:58 -06:00
e51ff44710
Added execution time information in logs
2019-08-21 11:08:47 -06:00
a335a57c6c
Added debug option to commnad line arguments
2019-08-21 11:08:13 -06:00
b7484ef178
Removed traces of old template file
2019-08-20 15:58:19 -06:00
08b0ef3550
Updated validate_command_line_arguments function
...
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
2019-08-19 21:28:23 -06:00
53941eaf5c
Changed yosys output file name
2019-08-19 19:06:46 -06:00
8f8707ff98
Added option to filter results after parsing
2019-08-19 19:04:14 -06:00
cb5b16c949
Moved required files to openfpga folder
2019-08-19 18:57:42 -06:00
7f6c1b3e00
Code re-arrangement
...
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
12c998c12a
Added dockerignore + minor changes in openfpga_flow script
2019-08-17 16:22:52 -06:00
c43c3cdf25
Added VPR output parse option
2019-08-16 13:36:39 -06:00
effbd332aa
Added task report generation
2019-08-16 10:59:44 -06:00
901932a4fc
First draft: Working openfpga task flow
2019-08-16 09:44:50 -06:00
5d3708651e
Added fpga_flow and fpga_task script
...
+ Missed local intermediate commits
2019-08-15 14:39:58 -06:00
9ab57d1b2e
Added fpga_flow script - Working Yosys
2019-08-09 16:49:05 -06:00
b82369dd96
Added first draft of fpga_task script
2019-08-09 00:17:06 -06:00
ganeshgore
tangxifan