tangxifan
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e633e3d17b
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update fpga_flow scripts to support vpr_only flow
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2019-07-11 19:40:58 -06:00 |
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tangxifan
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9c203ca4d2
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bug fixing in SDC generator
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2019-07-11 17:10:08 -06:00 |
AurelienUoU
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1848771e54
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Add explicit mapping option into fpga_flow
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2019-07-11 14:44:30 -06:00 |
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tangxifan
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31749fe62b
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fix bugs in fpga_flow.pl
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2019-07-10 21:12:00 -06:00 |
|
tangxifan
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206fc84a0e
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minor fix in fpga_flow
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2019-07-10 15:12:51 -06:00 |
|
AurelienUoU
|
b4a78abc04
|
Update doc
Merge remote-tracking branch 'origin/heterogeneous' into dev
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2019-07-05 12:25:37 -06:00 |
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tangxifan
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c8ceb8f7d5
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update fpga_flow.pl
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2019-07-04 12:23:11 -06:00 |
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tangxifan
|
5a50fa84d1
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keep updating fpga_flow.pl to use system call
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2019-07-03 22:57:43 -06:00 |
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tangxifan
|
6b894640c7
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bug fixing in fpga_flow.pl
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2019-07-03 14:59:05 -06:00 |
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tangxifan
|
5195faab8b
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Merge branch 'dev' into tileable_routing
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2019-07-03 14:30:39 -06:00 |
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tangxifan
|
4f3cb0bdf3
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added tileable routing chanW adaption to fixed W router
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2019-07-03 14:29:50 -06:00 |
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tangxifan
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c9743e84da
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-03 14:12:47 -06:00 |
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tangxifan
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a539c6a2a7
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bug fixing in fpga_flow.pl
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2019-07-03 14:11:14 -06:00 |
Ganesh Gore
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57ad71438b
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Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
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2019-07-03 13:39:52 -06:00 |
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AurelienUoU
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e13c703709
|
Upload recent commit
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-07-03 13:09:34 -06:00 |
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AurelienUoU
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43e9d8afd1
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Add compact routing hierarchy option in fpga_flow
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2019-07-03 13:08:49 -06:00 |
|
Ganesh Gore
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3c36a51011
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Added 'rewrite_path_in_file' back to repository
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2019-07-03 12:49:25 -06:00 |
|
Ganesh Gore
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53486b8a89
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Added 'spice_simulator_path' in fpga_flow
added vpr_fpga_spice_simulator_path in fpga-flow script
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2019-07-03 12:30:56 -06:00 |
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tangxifan
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0c3e8bb70a
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add a new option to the router to enable conversion of route_chan_width to be tileable
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2019-07-03 12:11:48 -06:00 |
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tangxifan
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02398818a9
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update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
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2019-07-03 10:33:02 -06:00 |
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tangxifan
|
4392c6bc3a
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bug fixing in fpga_flow scripts and add more print-out message for VPR
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2019-07-02 15:34:59 -06:00 |
|
Ganesh Gore
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54f6ca2687
|
Added lattice benchmark settings
|
2019-07-01 11:07:23 -06:00 |
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tangxifan
|
c54f3905d5
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fixed broken fpga flow
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2019-06-28 13:07:04 -06:00 |
|
AurelienUoU
|
c76dbaac33
|
Update regression test avoiding overwritting files
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2019-06-14 11:44:44 -06:00 |
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AurelienUoU
|
bf13c1f731
|
Add a script to create a new file with correct path rather than overwrite the existing
|
2019-06-11 14:28:58 -06:00 |
|
AurelienUoU
|
a2f6ded2a2
|
Add path modification in file changing a keyword into OpenFPGA full path
|
2019-06-04 15:21:15 -06:00 |
|
AurelienUoU
|
ba05a08ef0
|
Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
|
2019-05-30 09:52:19 -06:00 |
|
AurelienUoU
|
f934f6f0a3
|
Debug step
|
2019-05-28 15:01:16 -06:00 |
|
AurelienUoU
|
1018134726
|
Update yosys to latest version + add simulation in fpga_flow
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2019-05-23 17:55:49 -06:00 |
|
AurelienUoU
|
2b04376209
|
Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
|
2019-05-22 13:44:48 -06:00 |
|
AurelienUoU
|
b4c97f86a3
|
Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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2019-05-21 17:24:06 -06:00 |
|
AurelienUoU
|
199cd99b23
|
Add dummy clock name in ace2 commands
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2019-05-21 10:35:12 -06:00 |
|
AurelienUoU
|
2392d11790
|
Add debug command to understandn travis issue with ace
|
2019-05-20 16:06:37 -06:00 |
|
AurelienUoU
|
becb90cd16
|
Correct syntax error in ace2 log file generation
|
2019-05-20 13:56:50 -06:00 |
|
AurelienUoU
|
82c76a2c39
|
Test removing the shell specification in fpga_flow.pl
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2019-05-20 10:35:33 -06:00 |
|
AurelienUoU
|
43a64c26e8
|
Change tcsh to csh in fpga_flow.pl -> tcsh not found by travis
|
2019-05-20 09:44:38 -06:00 |
|
AurelienUoU
|
17ad905b14
|
Update flow and allow netlist generation
|
2019-05-17 17:00:38 -06:00 |
Baudouin Chauviere
|
0b1ccf7722
|
and in the config path as well
|
2018-12-06 14:57:32 -07:00 |
|
tangxifan
|
4f5f8de46f
|
Add Yosys and update flow_flow Perl Script
|
2018-11-30 21:14:43 -07:00 |
|
Baudouin Chauviere
|
d55ecd154b
|
Add the PTM to the benchmark flow
|
2018-11-21 11:32:34 -07:00 |
|
Baudouin Chauviere
|
8ce0a84bc1
|
Correction of the global make, the fpga_flow and the doc
|
2018-11-20 14:47:15 -07:00 |
|
Baudouin Chauviere
|
03e902023a
|
Perl script integrated to flow. rm shell one
|
2018-11-20 13:32:11 -07:00 |
|
Baudouin Chauviere
|
15d69e2bb1
|
Generation script finished TODO: integration in flow
|
2018-11-20 13:24:31 -07:00 |
|
Baudouin Chauviere
|
e74f05a161
|
Switching from sh to pl
|
2018-11-20 10:15:31 -07:00 |
Baudouin Chauviere
|
9611576d6a
|
Update on the examples to respect the new syntax
|
2018-11-19 15:50:29 -07:00 |
|
Baudouin Chauviere
|
9538dbd644
|
Config script written and changed some rights for some files
|
2018-10-24 15:59:32 -06:00 |
Xifan Tang
|
1cf066d3ad
|
Fixing minor bugs
|
2018-09-06 14:25:23 -06:00 |
|
Xifan Tang
|
42da9160f0
|
Clean codes and update
|
2018-09-04 17:49:20 -06:00 |
|
Xifan Tang
|
00ecd0bb1d
|
Cleanup codes and organization
|
2018-09-04 17:31:30 -06:00 |
|
Xifan Tang
|
cb15bb5082
|
Clean code and fix minor bugs
|
2018-08-10 13:46:00 -06:00 |