Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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AurelienUoU
parent
d10e05f5cc
commit
b4c97f86a3
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@ -11,12 +11,11 @@ elliptic/*.v, 300
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ex1010/*.v, 300
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ex5p/*.v, 300
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frisc/*.v, 300
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mcnc_big20.txt
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misex3/*.v, 300
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pdc/*.v, 300
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s298/*.v, 30
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s38417/*.v, 300
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s38584.1/*.v, 300
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s38584/*.v, 300
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seq/*.v, 300
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spla/*.v, 300
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tseng/*.v, 300
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@ -1,6 +1,6 @@
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// Benchmark "TOP" written by ABC on Tue Mar 5 09:55:28 2019
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module bigkey ( clock,
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module bigkey ( clk,
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Pstart_0_, Pkey_255_, Pkey_254_, Pkey_253_, Pkey_252_, Pkey_251_,
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Pkey_250_, Pkey_249_, Pkey_248_, Pkey_247_, Pkey_246_, Pkey_245_,
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Pkey_244_, Pkey_243_, Pkey_242_, Pkey_241_, Pkey_240_, Pkey_239_,
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@ -115,7 +115,7 @@ module bigkey ( clock,
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Pkey_17_, Pkey_16_, Pkey_15_, Pkey_14_, Pkey_13_, Pkey_12_, Pkey_11_,
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Pkey_10_, Pkey_9_, Pkey_8_, Pkey_7_, Pkey_6_, Pkey_5_, Pkey_4_,
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Pkey_3_, Pkey_2_, Pkey_1_, Pkey_0_, Pencrypt_0_, Pcount_3_, Pcount_2_,
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Pcount_1_, Pcount_0_, clock;
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Pcount_1_, Pcount_0_, clk;
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output Pnew_count_3_, Pnew_count_2_, Pnew_count_1_, Pnew_count_0_,
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Pdata_ready_0_, PKSi_191_, PKSi_190_, PKSi_189_, PKSi_188_, PKSi_187_,
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PKSi_186_, PKSi_185_, PKSi_184_, PKSi_183_, PKSi_182_, PKSi_181_,
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@ -1966,7 +1966,7 @@ module bigkey ( clock,
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assign PKSi_139_ = \[282] ;
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assign PKSi_90_ = \[333] ;
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assign PKSi_88_ = \[333] ;
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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PKSi_79_ <= n921;
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PKSi_92_ <= n925_1;
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\[333] <= n929_1;
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@ -1,6 +1,6 @@
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// Benchmark "TOP" written by ABC on Tue Mar 5 09:55:52 2019
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module clma ( clock,
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module clma ( clk,
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Pi416, Pi415, Pi414, Pi413, Pi412, Pi411, Pi410, Pi409, Pi408, Pi407,
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Pi406, Pi405, Pi404, Pi403, Pi402, Pi401, Pi400, Pi399, Pi398, Pi397,
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Pi396, Pi395, Pi394, Pi393, Pi392, Pi391, Pi390, Pi389, Pi388, Pi387,
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@ -93,7 +93,7 @@ module clma ( clock,
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Pi73, Pi72, Pi71, Pi70, Pi69, Pi68, Pi67, Pi66, Pi65, Pi64, Pi63, Pi62,
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Pi61, Pi60, Pi59, Pi58, Pi57, Pi56, Pi55, Pi54, Pi53, Pi52, Pi51, Pi50,
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Pi49, Pi28, Pi27, Pi26, Pi25, Pi24, Pi23, Pi22, Pi21, Pi20, Pi19, Pi18,
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Pi17, Pi16, Pi15, clock;
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Pi17, Pi16, Pi15, clk;
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output P__cmxir_1, P__cmxir_0, P__cmxig_1, P__cmxig_0, P__cmxcl_1,
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P__cmxcl_0, P__cmx1ad_35, P__cmx1ad_34, P__cmx1ad_33, P__cmx1ad_32,
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P__cmx1ad_31, P__cmx1ad_30, P__cmx1ad_29, P__cmx1ad_28, P__cmx1ad_27,
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@ -4736,7 +4736,7 @@ module clma ( clock,
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assign n4774 = n3984 | n4726 | n4727;
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assign n4775 = n3669 & Pi27;
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assign n1085 = P__cmxcl_0;
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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Ni48 <= n931_1;
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Ni47 <= n936;
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Ni46 <= n941_1;
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@ -1,6 +1,6 @@
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// Benchmark "TOP" written by ABC on Tue Mar 5 09:56:39 2019
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module diffeq ( clock,
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module diffeq ( clk,
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PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_, Pdxport_3_3_,
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Pdxport_4_4_, Pdxport_5_5_, Pdxport_6_6_, Pdxport_7_7_, Pdxport_8_8_,
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Pdxport_9_9_, Pdxport_10_10_, Pdxport_11_11_, Paport_0_0_, Paport_1_1_,
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@ -8,7 +8,7 @@ module diffeq ( clock,
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Paport_7_7_, Paport_8_8_, Paport_9_9_, Paport_10_10_, Paport_11_11_,
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Preset_0_0_, Pready_0_0_,
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PDN, Pnext_0_0_, Pover_0_0_ );
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input clock, PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_,
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input clk, PRESET, Pdxport_0_0_, Pdxport_1_1_, Pdxport_2_2_,
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Pdxport_3_3_, Pdxport_4_4_, Pdxport_5_5_, Pdxport_6_6_, Pdxport_7_7_,
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Pdxport_8_8_, Pdxport_9_9_, Pdxport_10_10_, Pdxport_11_11_,
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Paport_0_0_, Paport_1_1_, Paport_2_2_, Paport_3_3_, Paport_4_4_,
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@ -1211,7 +1211,7 @@ module diffeq ( clock,
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assign n1991 = n1858 ^ n1859;
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assign n1992 = n1975 & n1555_1 & n1552 & n1546 & ~N_N3999 & n1519 & n1543 & n1549;
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assign n1993 = ~Preset_0_0_ & n1833;
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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N_N4054 <= n63_1;
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N_N3745 <= n68_1;
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N_N4119 <= n73_1;
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@ -1,6 +1,6 @@
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// Benchmark "top" written by ABC on Tue Mar 5 10:01:57 2019
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module dsip ( clock,
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module dsip ( clk,
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pcount_3_, pkey_5_, pkey_131_, pkey_144_, pkey_157_, pkey_230_,
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pkey_243_, pcount_2_, pkey_4_, pkey_132_, pkey_158_, pkey_169_,
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pkey_242_, pcount_1_, pkey_146_, pkey_168_, pkey_245_, pcount_0_,
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@ -94,7 +94,7 @@ module dsip ( clock,
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pkey_133_, pkey_142_, pkey_218_, pkey_227_, pkey_232_, pkey_241_,
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pkey_2_, pkey_99_, pkey_134_, pkey_141_, pkey_219_, pkey_226_,
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pkey_233_, pkey_240_, pkey_70_, pkey_81_, pkey_92_, pkey_180_,
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pkey_193_, pkey_80_, pkey_93_, pkey_107_, pkey_194_, pkey_206_, clock,
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pkey_193_, pkey_80_, pkey_93_, pkey_107_, pkey_194_, pkey_206_, clk,
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pkey_50_, pkey_61_, pkey_94_, pkey_182_, pkey_195_, pkey_209_,
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pstart_0_, pkey_51_, pkey_60_, pkey_109_, pkey_181_, pkey_196_,
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pkey_208_, pkey_52_, pkey_74_, pkey_85_, pkey_104_, pkey_171_,
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@ -1686,7 +1686,7 @@ module dsip ( clock,
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assign n2465 = ~pencrypt_0_ & ~pstart_0_ & ~pcount_1_ & ~pcount_0_;
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assign n2466 = pcount_2_ ? ~pencrypt_0_ : (~pstart_0_ & pencrypt_0_);
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assign n2467 = n1341 | ~n1330 | (~pcount_2_ & n1329);
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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pksi_17_ <= n853;
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pksi_185_ <= n857;
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n_n2410 <= n861;
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@ -1,6 +1,6 @@
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// Benchmark "top" written by ABC on Thu Feb 21 17:22:32 2019
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module elliptic ( clock,
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module elliptic ( clk,
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tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_,
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tin_psv2_8_8_, pinp_2_2_, tin_psv38_2_2_, tin_psv33_5_5_,
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tin_psv26_6_6_, tin_psv2_9_9_, pinp_3_3_, tin_psv18_2_2_,
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@ -55,7 +55,7 @@ module elliptic ( clock,
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psv18_8_8_, psv18_0_0_, psv39_7_7_, psv13_4_4_, psv2_2_2_, psv38_9_9_,
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psv38_1_1_, psv39_15_15_, psv33_4_4_, psv26_5_5_, psv2_3_3_,
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psv38_13_13_, psv18_14_14_, psv18_9_9_, psv18_1_1_ );
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input clock, tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_,
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input clk, tin_psv39_8_8_, tin_psv39_0_0_, tin_psv13_5_5_, tin_psv2_13_13_,
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tin_psv2_8_8_, pinp_2_2_, tin_psv38_2_2_, tin_psv33_5_5_,
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tin_psv26_6_6_, tin_psv2_9_9_, pinp_3_3_, tin_psv18_2_2_,
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tin_psv39_9_9_, tin_psv39_1_1_, tin_psv13_6_6_, tin_psv2_6_6_,
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@ -4214,7 +4214,7 @@ module elliptic ( clock,
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assign n7210 = pdn | preset | (nsr3_37 & ~nen3_34);
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assign n7211 = pdn | preset | (~nak3_13 & nsr3_20);
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assign n7212 = n_n8419 & n4856 & (n7118 | n7119);
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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n_n9280 <= n491;
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n_n9172 <= n496;
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n_n9260 <= n501;
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@ -2,7 +2,7 @@
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module frisc (
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tin_pdata_8_8_, tin_pdata_0_0_, tin_pdata_7_7_, preset_0_0_,
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tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, pclk,
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tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, clk,
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pirq_0_0_, tin_pdata_10_10_, tin_pdata_3_3_, tin_pdata_6_6_,
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tin_pdata_15_15_, tin_pdata_11_11_, tin_pdata_14_14_, tin_pdata_12_12_,
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tin_pdata_5_5_, preset, tin_pdata_13_13_,
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@ -31,7 +31,7 @@ module frisc (
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pdata_14_14_, pdata_12_12_, pdata_5_5_, ppeakb_6_6_, ppeaka_6_6_,
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ppeaks_11_11_, ppeaki_12_12_, ppeaki_2_2_, paddress_0_0_, pdata_13_13_ );
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input tin_pdata_8_8_, tin_pdata_0_0_, tin_pdata_7_7_, preset_0_0_,
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tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, pclk,
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tin_pdata_2_2_, tin_pdata_9_9_, tin_pdata_1_1_, tin_pdata_4_4_, clk,
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pirq_0_0_, tin_pdata_10_10_, tin_pdata_3_3_, tin_pdata_6_6_,
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tin_pdata_15_15_, tin_pdata_11_11_, tin_pdata_14_14_, tin_pdata_12_12_,
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tin_pdata_5_5_, preset, tin_pdata_13_13_;
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@ -4101,7 +4101,7 @@ module frisc (
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assign n6330 = ~preset & n3798 & (\[17050] | \[17102] );
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assign n6331 = n6330 | n3969 | n6325;
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assign n6332 = n6326 | n6327 | n6328 | n6329;
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always @ (posedge pclk) begin
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always @ (posedge clk) begin
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ndout <= n273;
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ppeakb_12_12_ <= n278;
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ppeakb_1_1_ <= n282;
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@ -1,9 +1,9 @@
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// Benchmark "s298.bench" written by ABC on Tue Mar 5 10:03:54 2019
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module s298 ( clock,
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module s298 ( clk,
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G0, G1, G2,
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G117, G132, G66, G118, G133, G67 );
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input G0, G1, G2, clock;
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input G0, G1, G2, clk;
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output G117, G132, G66, G118, G133, G67;
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reg G10, G11, G12, G13, G14, G15, G16, G17, G18, G19, G20, G21, G22, G23;
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wire n57, n59, n64, n66, n21_1, n26_1, n31_1, n36_1, n41_1, n46_1, n51_1,
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@ -32,7 +32,7 @@ module s298 ( clock,
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assign G118 = G19;
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assign G133 = G21;
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assign G67 = G17;
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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G10 <= n21_1;
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G11 <= n26_1;
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G12 <= n31_1;
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@ -1,6 +1,6 @@
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// Benchmark "TOP" written by ABC on Tue Mar 5 10:04:28 2019
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module s38417 ( clock,
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module s38417 ( clk,
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Pg3234, Pg3233, Pg3232, Pg3231, Pg3230, Pg3229, Pg3228, Pg3227, Pg3226,
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Pg3225, Pg3224, Pg3223, Pg3222, Pg3221, Pg3220, Pg3219, Pg3218, Pg3217,
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Pg3216, Pg3215, Pg3214, Pg3213, Pg3212, Pg2637, Pg1943, Pg1249, Pg563,
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@ -20,7 +20,7 @@ module s38417 ( clock,
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input Pg3234, Pg3233, Pg3232, Pg3231, Pg3230, Pg3229, Pg3228, Pg3227,
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Pg3226, Pg3225, Pg3224, Pg3223, Pg3222, Pg3221, Pg3220, Pg3219, Pg3218,
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Pg3217, Pg3216, Pg3215, Pg3214, Pg3213, Pg3212, Pg2637, Pg1943, Pg1249,
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Pg563, Pg51, clock;
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Pg563, Pg51, clk;
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output Pg27380, Pg26149, Pg26135, Pg26104, Pg25489, Pg25442, Pg25435,
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Pg25420, Pg24734, Pg16496, Pg16437, Pg16399, Pg16355, Pg16297, Pg8275,
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Pg8274, Pg8273, Pg8272, Pg8271, Pg8270, Pg8269, Pg8268, Pg8267, Pg8266,
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@ -5262,7 +5262,7 @@ module s38417 ( clock,
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assign n7160 = Pg3234;
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assign n7163 = Pg5388;
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assign n7167 = Pg16496;
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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Pg8021 <= n270_1;
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Ng2817 <= n274_1;
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Ng2933 <= n279_1;
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@ -1,6 +1,6 @@
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// Benchmark "TOP" written by ABC on Tue Mar 5 10:05:28 2019
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module s38584 ( clock,
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module s38584 ( clk,
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Pg6753, Pg6752, Pg6751, Pg6750, Pg6749, Pg6748, Pg6747, Pg6746, Pg6745,
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Pg6744, Pg135, Pg134, Pg127, Pg126, Pg125, Pg124, Pg120, Pg116, Pg115,
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Pg114, Pg113, Pg100, Pg99, Pg92, Pg91, Pg90, Pg84, Pg73, Pg72, Pg64,
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@ -46,7 +46,7 @@ module s38584 ( clock,
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input Pg6753, Pg6752, Pg6751, Pg6750, Pg6749, Pg6748, Pg6747, Pg6746,
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Pg6745, Pg6744, Pg135, Pg134, Pg127, Pg126, Pg125, Pg124, Pg120, Pg116,
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Pg115, Pg114, Pg113, Pg100, Pg99, Pg92, Pg91, Pg90, Pg84, Pg73, Pg72,
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Pg64, Pg57, Pg56, Pg54, Pg53, Pg44, Pg36, Pg35, Pg5, clock;
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Pg64, Pg57, Pg56, Pg54, Pg53, Pg44, Pg36, Pg35, Pg5, clk;
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output Pg34972, Pg34956, Pg34927, Pg34925, Pg34923, Pg34921, Pg34919,
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Pg34917, Pg34915, Pg34913, Pg34839, Pg34788, Pg34597, Pg34437, Pg34436,
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Pg34435, Pg34425, Pg34383, Pg34240, Pg34239, Pg34238, Pg34237, Pg34236,
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@ -6408,7 +6408,7 @@ module s38584 ( clock,
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assign n6526 = Pg8789;
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assign n6555 = Pg9555;
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assign n6642 = Pg8786;
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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Ng5057 <= n687;
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Ng2771 <= n692_1;
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Ng1882 <= n697_1;
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@ -1,6 +1,6 @@
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// Benchmark "top" written by ABC on Tue Mar 5 10:05:48 2019
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module tseng ( clock,
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module tseng ( clk,
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tin_pv10_4_4_, tin_pv11_4_4_, tin_pv6_7_7_, tin_pv2_0_0_,
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tin_pv10_3_3_, tin_pv1_2_2_, tin_pv11_3_3_, tin_pv4_3_3_,
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tin_pv10_2_2_, tin_pv11_2_2_, tin_pv6_0_0_, tin_pv2_1_1_,
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@ -40,7 +40,7 @@ module tseng ( clock,
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tin_pready_0_0_, tin_pv10_0_0_, tin_pv11_0_0_, tin_pv6_1_1_,
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tin_pv2_2_2_, tin_pv1_4_4_, tin_pv4_5_5_, tin_pv6_2_2_, tin_pv2_3_3_,
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tin_pv1_5_5_, tin_pv4_6_6_, tin_pv6_3_3_, tin_pv2_4_4_, tin_pv1_6_6_,
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clock, tin_pv4_7_7_, tin_pv6_4_4_, tin_pv2_5_5_, tin_pv1_7_7_,
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clk, tin_pv4_7_7_, tin_pv6_4_4_, tin_pv2_5_5_, tin_pv1_7_7_,
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tin_pv4_0_0_, tin_pv6_5_5_, tin_pv2_6_6_, tin_pv10_7_7_, tin_pv1_0_0_,
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tin_pv11_7_7_, tin_pv4_1_1_, tin_pv10_6_6_, tin_pv11_6_6_,
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tin_pv6_6_6_, tin_pv2_7_7_, preset, tin_pv10_5_5_, tin_pv1_1_1_,
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@ -1256,7 +1256,7 @@ module tseng ( clock,
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assign n2372 = n2331 & ~n1937 & ~preset & n_n3709;
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assign n2373 = n1849 & ~n_n4067;
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assign n2374 = ~n2310 & n1903_1 & n_n4093 & ~n1897;
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always @ (posedge clock) begin
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always @ (posedge clk) begin
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||||
n_n4142 <= n349;
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||||
n_n3936 <= n354;
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n_n3574 <= n359;
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||||
|
|
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|||
|
|
@ -1205,7 +1205,7 @@ sub run_ace($ $ $ $) {
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|||
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||||
print "Entering $ace_dir\n";
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||||
chdir $ace_dir;
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||||
system("./$ace_name -b $mpack_vpr_blif -o $act_file -n $ace_new_blif -c avoid_clk_option $ace_customized_opts >> $log");
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||||
system("./$ace_name -b $mpack_vpr_blif -o $act_file -n $ace_new_blif -c clk $ace_customized_opts >> $log");
|
||||
|
||||
if (!(-e $ace_new_blif)) {
|
||||
die "ERROR: Fail ACE for benchmark $mpack_vpr_blif.\n";
|
||||
|
|
@ -1778,9 +1778,11 @@ sub run_yosys_vpr_flow($ $ $ $ $)
|
|||
&run_yosys_fpgamap($benchmark, $yosys_bm, $yosys_blif_out, $yosys_log);
|
||||
|
||||
# Files for ace
|
||||
my ($act_file,$ace_new_blif,$ace_log) = ("$rpt_dir/$benchmark".".act","$rpt_dir/$benchmark".".blif","$prefix"."ace.log");
|
||||
my ($act_file,$ace_new_blif,$ace_log, $corrected_ace_blif) = ("$rpt_dir/$benchmark".".act","$rpt_dir/$benchmark"."ace.blif","$prefix"."ace.log","$rpt_dir/$benchmark".".blif");
|
||||
&run_ace_in_flow($prefix, $yosys_blif_out, $act_file, $ace_new_blif, $ace_log);
|
||||
|
||||
&run_pro_blif($ace_new_blif, $corrected_ace_blif);
|
||||
|
||||
# Files for VPR
|
||||
my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log);
|
||||
|
||||
|
|
@ -1793,7 +1795,7 @@ sub run_yosys_vpr_flow($ $ $ $ $)
|
|||
# Need to add a regenation of the verilog from the optimized blif -> write verilog from blif + correct the name of the verilog for the testbench
|
||||
$verilog_benchmark = &run_rewrite_verilog($ace_new_blif, $rpt_dir, $benchmark, $benchmark, $yosys_log);
|
||||
|
||||
&run_vpr_in_flow($tag, $benchmark, $benchmark_file, $ace_new_blif, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results);
|
||||
&run_vpr_in_flow($tag, $benchmark, $benchmark_file, $corrected_ace_blif, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue